A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

A method, comprising: receiving a video comprising video frames as an input; generating set of object proposals from the video; generating object tracklets comprising regions appearing in consecutive frames of the video, said regions corresponding to object proposals with a predetermined level of confidence; constructing a graph comprising the object proposals and superpixels grouped from the pixels of the frame; calculating a first cost function for superpixel likelihoods in terms of the object proposals in an object tracklet; calculating a second cost function for object proposal likelihoods in terms of the superpixels in the frame; minimizing the first and the second cost function with each other; computing posterior probabilities of each superpixel; and assigning each superpixel with an object class with a maximum posterior probability to constitute semantic object segmentation.

A method, comprising: receiving a video comprising video frames as an input; generating set of object proposals from the video; generating object tracklets comprising regions appearing in consecutive frames of the video, said regions corresponding to object proposals with a predetermined level of confidence; constructing a graph comprising the object proposals and superpixels grouped from the pixels of the frame; calculating a first cost function for superpixel likelihoods in terms of the object proposals in an object tracklet; calculating a second cost function for object proposal likelihoods in terms of the superpixels in the frame; minimizing the first and the second cost function with each other; computing posterior probabilities of each superpixel; and assigning each superpixel with an object class with a maximum posterior probability to constitute semantic object segmentation.

A method for performing a write operation in a distributed storage system is disclosed. The method comprises receiving a first time-stamped write request from a proxy server. Further, the method comprises determining if the first time-stamped write request is within a time window of a reorder buffer and if the first time-stamped write request overlaps with a second time-stamped write request in the reorder buffer. Responsive to a determination that the first time-stamped write request is outside the time window or that the first time-stamped write request is within the time window but has an older time-stamp than the second time-stamped write request, the method comprises rejecting the first time-stamped write request. Otherwise, the method comprises inserting the first time-stamped write request in the reorder buffer in timestamp order and transmitting an accept to the proxy server.

A storage device allocates an address area of an address space to the first virtual address space in accordance with writing onto a first virtual address space. A controller manages an address area in the first virtual address space, in which address area a mapping to the real address space has been removed, as a usage prohibition area. When a use state of the first virtual address space reaches a predetermined criterion, the controller or the storage device adds new continuous address areas to the first virtual address space to expand the first virtual address space. The storage device allocates an area, in which a mapping to the first virtual address space has been removed, to the first virtual address space expanded.

A storage device allocates an address area of an address space to the first virtual address space in accordance with writing onto a first virtual address space. A controller manages an address area in the first virtual address space, in which address area a mapping to the real address space has been removed, as a usage prohibition area. When a use state of the first virtual address space reaches a predetermined criterion, the controller or the storage device adds new continuous address areas to the first virtual address space to expand the first virtual address space. The storage device allocates an area, in which a mapping to the first virtual address space has been removed, to the first virtual address space expanded.

Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.

Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.

A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.