A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree. The delay circuit causes the state-overlap to exceed the tree propagation time.

An electronic device including a display; and a controller configured to display a playback screen of virtual reality content on the display, in response to a capture command while displaying the playback screen of the virtual reality content, display a virtual icon on the playback screen, and in response to a touch input applied to the virtual icon, capture an image of a virtual space of the virtual reality content based on a position of a user in the virtual space and corresponding to a touch level of the touch input.

Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

A modular system including a set of functionality tiles and a control tile storing a storage structure, an initialization file, and operation instructions. The method for operating a custom device made using the modular system includes: sending operation settings for each tile to the respective tile upon device initialization; operating each tile based on the operation settings; writing the output from each tile to the storage structure; monitoring data streams within the storage structure for a trigger event; reading data off the storage structure in response to occurrence of the trigger event; and processing the read data according to a processing function specified by the operation instructions.

Techniques are disclosed for power conservation. A plurality of processing elements and a plurality of instructions are configured. The plurality of processing elements is controlled by instructions contained in a plurality of circular buffers. The plurality of processing elements can comprise a data flow processor. A first processing element, from the plurality of interconnected processing elements, is set into a sleep state by a first instruction from the plurality of instructions. The first processing element is woken from the sleep state as a result of valid data being presented to the first processing element. A subsection of the plurality of interconnected processing elements is also set into a sleep state based on the first processing element being set into a sleep state. At least one circular buffer from the plurality of circular buffers remains awake while the first processing element is in the sleep state, and the at least one circular buffer provides for data steering through a reconfigurable fabric.

A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

A method of storing information using monomers such as nucleotides is provided including converting a format of information into a plurality of bit sequences of a bit stream with each having a corresponding bit barcode, converting the plurality of bit sequences to a plurality of corresponding oligonucleotide sequences using one bit per base encoding, synthesizing the plurality of corresponding oligonucleotide sequences on a substrate having a plurality of reaction locations, and storing the synthesized plurality of corresponding oligonucleotide sequences.