Methods and apparatus for piecewise addition into an accumulation register using one or more carry runway registers, where the accumulation register includes a first plurality of qubits with each qubit representing a respective bit of a first binary number and where each carry runway register includes multiple qubits representing a respective binary number. In one aspect, a method includes inserting the one or more carry runway registers into the accumulation register at respective predetermined qubit positions, respectively, of the accumulation register; initializing each qubit of each carry runway register in a plus state; applying one or more subtraction operations to the accumulation register, where each subtraction operation subtracts a state of a respective carry runway register from a corresponding portion of the accumulation register; and adding one or more input binary numbers into the accumulation register using piecewise addition.

Systems, apparatuses and methods may provide for technology that conducts, by a differential signal path, signed multiply-accumulate (MAC) operations on first analog signals and multibit weight data stored in the differential signal path, and outputs, by the differential signal path, second analog signals based on the signed MAC operations.

Methods and systems of reducing power transmitted over a memory to cache bus having a plurality of cache lines by identifying floating point numbers transmitted over a cache line, rounding bits in least significant bit (LSB) positions of identified floating point (FP) numbers to a uniform binary value string, mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each FP number to increase a chance of matching bit patterns between pairs of the FP numbers, and compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process. A decompressor decompresses the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and the mapping component applies a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions to recover the original floating point numbers.

Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Systems and methods of the present invention provide for one or more server computers communicatively coupled to a network and configured to: receive a request to execute a computational task, including a transformed input used to execute a computational task. A client computer transforms the original input into the transformed input, using an affine mapping where the transformed input is a one-to-one equivalent to the original input (but which can't be inferred by the server computer), and according to a user selection limiting the computational complexity of the mapping according to resource constraints on the client. The server may then execute the computational task and transmit a result to the client to apply an inverse affine mapping, and receive a response which verifies that the computational task result is complete and valid.

Systems and methods of the present invention provide for one or more server computers communicatively coupled to a network and configured to: receive a request to execute a computational task, including a transformed input used to execute a computational task. A client computer transforms the original input into the transformed input, using an affine mapping where the transformed input is a one-to-one equivalent to the original input (but which can't be inferred by the server computer), and according to a user selection limiting the computational complexity of the mapping according to resource constraints on the client. The server may then execute the computational task and transmit a result to the client to apply an inverse affine mapping, and receive a response which verifies that the computational task result is complete and valid.

An arithmetic apparatus used for a neural network includes a plurality of digital-time conversion circuits connected in series and a time-digital conversion circuit connected to a last digital-time conversion circuit in the series. Each of the digital-time conversion circuits is configured to delay a first input time signal by a variable amount, delay a second input time signal by a fixed amount, and output the delayed first and second input time signals respectively as either first and second output time signals or second and first output time signals, in accordance with the input data. The time-digital conversion circuit is configured to generate a digital output signal by comparing first and second output time signals from the last digital-time conversion circuit.

Provided are embodiments for a circuit comprising for performing hardware acceleration for elliptic curve cryptography (ECC). The circuit includes a code array comprising instructions for performing complex modular arithmetic; and a data array storing values corresponding to one or more complex numbers. The modular arithmetic unit includes a first multiplier and a first accumulation unit, a second multiplier and a second accumulation unit, and a third multiplier and a third accumulation unit, wherein the first, second, and third multiplier and accumulation units are cascaded and configured to perform hardware computation of complex modular operations. Also provided are embodiments of a computer program product and a method for performing the hardware acceleration of super-singular isogeny key encryption (SIKE) operations.

Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.