An individual neuron circuit calculates a first value based on a sum of products each obtained by multiplying one of weight values, each representing connection or disconnection between a corresponding neuron circuit and one of the other neuron circuits, by a corresponding one of output signals of the other neuron circuits and outputs 0 or 1, based on a result of comparison between a second value obtained by adding a noise value to the first value and a threshold. An arbitration circuit allows, when first output signals of first neuron circuits interconnected among the neuron circuits simultaneously change based on the weight values, updating of only one of the first output signals of the first neuron circuits and allows, when second output signals of second neuron circuits not interconnected simultaneously change, updating of the second output signals.

A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B = 2.sup.ew-1 - 1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew - 1), bitwidth(iw - 2 - s.sub.y)} ≤ k ≤ (ew - 1) where s.sub.y = 1 for a signed floating point number and s.sub.y = 0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

Methods and apparatus for performing surface code computations using Auto-CCZ states. In one aspect, a method for implementing a delayed choice CZ operation on a first and second data qubit using a quantum computer includes: preparing a first and second routing qubit in a magic state; interacting the first data qubit with the first routing qubit and the second data qubit with the second routing qubit using a first and second CNOT operation, where the first and second data qubits act as controls for the CNOT operations; if a received first classical bit represents an off state: applying a first and second Hadamard gate to the first and second routing qubit; measuring the first and second routing qubit using Z basis measurements to obtain a second and third classical bit; and performing classically controlled fixup operations on the first and second data qubit using the second and third classical bits.

A computer for executing a computation algorithm involving a digital variable as per at least two operating phases is provided. The computer includes a memory stage having: a first set of memories for storing a first sub-word of each digital variable; with each memory of the first set being non-volatile and having a first read endurance and a first write cyclability; a second set of memories for storing a second sub-word of each digital variable; with each memory of the second set having a second read endurance and a second write cyclability; with the first read endurance being greater than the second read endurance and the first write cyclability being less than the second write cyclability.

A computer for executing a computation algorithm involving a digital variable as per at least two operating phases is provided. The computer includes a memory stage having: a first set of memories for storing a first sub-word of each digital variable; with each memory of the first set being non-volatile and having a first read endurance and a first write cyclability; a second set of memories for storing a second sub-word of each digital variable; with each memory of the second set having a second read endurance and a second write cyclability; with the first read endurance being greater than the second read endurance and the first write cyclability being less than the second write cyclability.

An electronic neuron device that includes a thresholding unit which utilizes current-induced spin-orbit torque (SOT). A two-step switching scheme is implemented with the device. In the first step, a charge current through heavy metal (HM) places the magnetization of a nano-magnet along the hard-axis (i.e. an unstable point for the magnet). In the second step, the device receives a current (from an electronic synapse) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the net synaptic current determines the final orientation of the magnetization. A resistive crossbar array may also be provided which functions as the synapse generating a bipolar current that is a weighted sum of the inputs of the device.

A coil spring modeling apparatus includes a first attachment member disposed on a lower spring seat, a second attachment member disposed on an upper spring seat, an actuator unit formed of a Stewart-platform-type parallel mechanism, a spring height detection mechanism, and a controller. The spring height detection mechanism is constituted of displacement gauges such as a linear variable differential transformer. These gauges are provided on hydraulic cylinders, and detect amounts of displacement relative to the reference lengths of the hydraulic cylinders, respectively. A hydraulic pressure supply device is controlled by the controller and supplies fluid pressure according to the displacement detected by the gauges to the respective hydraulic cylinders.

A hardware-based programmable deep learning processor (DLP) is proposed, wherein the DLP comprises with a plurality of accelerators dedicated for deep learning processing. Specifically, the DLP includes a plurality of tensor engines configured to perform operations for pattern recognition and classification based on a neural network. Each tensor engine includes one or more matrix multiplier (MatrixMul) engines each configured to perform a plurality of dense and/or sparse vector-matrix and matrix-matrix multiplication operations, one or more convolutional network (ConvNet) engines each configured to perform a plurality of efficient convolution operations on sparse or dense matrices, one or more vector floating point units (VectorFPUs) each configured to perform floating point vector operations, and a data engine configured to retrieve and store multi-dimensional data to both on-chip and external memories.

Methods and systems are provided for noise suppression in data, particularly data comprising video and/or audio data. An input adjustment, based on a corresponding input adjustment value, may be applied to received input data that comprises video and/or audio data; and an output adjustment, based on a corresponding output adjustment value, may be applied to output data corresponding to previously processed received input data. The input adjustment value may be re-calculated based on an outcome of applying the input adjustment to the received data, and when a change occurs in the input adjustment value the change in the input adjustment value may be applied to subsequent received input data, and at the same time, and based on the change in the input adjustment value, a corresponding change may be applied at least some of data corresponding to previously processed received input data.