The present disclosure is directed to systems and methods for a memory device such as, for example, a Processing-In-Memory Device that is configured to perform multiplication operations in memory using a popcount operation. A multiplication operation may include a summation of multipliers being multiplied with corresponding multiplicands. The inputs may be arranged in particular configurations within a memory array. Sense amplifiers may be used to perform the popcount by counting active bits along bit lines. One or more registers may accumulate results for performing the multiplication operations.

A monotonic counter memory system including a counter circuit and a memory circuit is provided. The counter circuit is configured to increase a count by one in response to a clock signal and output a count value of n bits, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The stored count value changes one bit at each input count of the clock signal, and a bit switching time of the stored count value are smaller than 2.sup.n1 times.

Providing neural network output values by receiving a neural network having defined node weights, determining network activations according to network input data, for each activation x of the network activations and each node weight w of the defined node weights: generating an activation sequence which is a unary representation of x/n.sub.x, a first weight sequence W.sub.L, and a second weight sequence W.sub.R, where the sequence W=(W.sub.n.sub.w, W.sub.n.sub.w.sub.?1, . . . , W.sub.2, W.sub.1, W.sub.0) is a unary representation of w/n.sub.w, the sequence V=(w.sub.0, W.sub.1, W.sub.2, . . . , W.sub.n.sub.w.sub.?1, W.sub.n.sub.w) is the reverse of W, and n.sub.x is a multiple of n.sub.w so that W.sub.L and W.sub.R are of length n.sub.x; and computing M.sub.S(X, W.sub.L)+M.sub.S(X, W.sub.R) as an approximation for 2(x/n.sub.x)(w/n.sub.w), wherein M.sub.S(.,.) denotes stochastic multiplication, and providing a neural network output based on, at least in part, a set of computed approximations for 2(x/n.sub.x)(w/n.sub.w) values.

A semiconductor cell comprising a memory element for storing a first binary operand is disclosed. In one aspect, the memory element provides complementary memory outputs, and a multiplication block that is locally and uniquely associated with the memory element. The multiplication block may be configured to receive complementary input signals representing binary input data and the complementary memory outputs of the associated memory element representing the first binary operand, implement a multiplication operation on these signals, and provide an output of the multiplication operation to an output port. An array of semiconductor cells and a neural network circuit comprising such array are also disclosed.

An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

Technical solutions are described for determining a population count of an input bit-string. In an example, a population count circuit receives a single n-bit input data word including of bits A[n1:0]. The population count circuit isolates a pair of 4-bit nibbles. The population count circuit includes a carryless counter circuit that determines a pair of counts of 1s, one for each 4-bit nibble. The population circuit further includes an adder circuit that determines the population count by summing the pair of counts of 1s from the carryless counter circuit, where the adder circuit determines the most significant bit (MSB) of the sum based on the MSBs of the counts of 1s only, without depending on carry propagation.

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

A processor includes a crossbar array including row wires and column wires wherein bit patterns representative of numerical values are stored in a plurality of columns of the crossbar array in the form of high or low resistance states. An output unit electrically connected to the rows of the crossbar array is configured to sum the numerical values stored in the columns of the crossbar array.

Technical solutions are described for determining a population count of an input bit-string. In an example, a population count circuit receives a single n-bit input data word including of bits A[n1:0]. The population count circuit isolates a pair of 4-bit nibbles. The population count circuit includes a carryless counter circuit that determines a pair of counts of 1s, one for each 4-bit nibble. The population circuit further includes an adder circuit that determines the population count by summing the pair of counts of 1s from the carryless counter circuit, where the adder circuit determines the most significant bit (MSB) of the sum based on the MSBs of the counts of 1s only, without depending on carry propagation.