Emulating a heterogeneous application having a kernel designated for hardware acceleration may include compiling, using a processor, host program code into a host binary configured to execute in a first process of a computing system and generating, using the processor, a device program binary implementing a register transfer level simulator using the kernel. The device program binary may be configured to execute in a second, different process of the computing system. A high level programming language model of static circuitry of a programmable integrated circuit that couples to a circuit implementation of the kernel may be compiled into a static circuitry binary. The static circuitry binary may be used by the register transfer level simulator during emulation.

Improved computer-implemented tools for use in modeling/simulating spatial charge distributions for electrophysiological systems are provided. The improvements are in three areas: (1) the use of solid angles to calculate quantities of free charge and/or bound charge in calculation cells and/or the movement of quantities of free charge across one or more faces of a calculation cell; (2) the use of flattened calculations cells having only two faces with substantial areas as seen from the free charge and/or the bound charge of the electrophysiological system; and (3) the use of at least two spatial charge distributions, specifically, at least one for bound charge and at least one for free charge, so as to include the effects of relative dielectric constants greater than 1.0 for part or all of an electrophysiological system. The three improvements can be used individually or in combinations.

A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

An electric vehicle motor rotational speed value generating device comprises: a first counter counting an input frequency according to a system frequency and outputs a first bit numerical value; a second counter receiving the first bit numerical value, the second counter counts the first bit numerical value with an exponent n in a 2.sup.n exponential function that approximates a maximum rotational speed command value and outputs a second bit numerical value; a frequency divider receiving the second bit numerical value, and the frequency divider divides the second bit numerical value from the system frequency and outputs a counting frequency; and a third counter receiving the counting frequency, and the third counter is electrically connected to a maximum frequency generator and receives a maximum frequency generated by the maximum frequency generator, and the third counter counts the maximum frequency from the counting frequency and outputs a feedback rotational speed value.

An electric vehicle motor rotational speed value generating device comprises: a first counter counting an input frequency according to a system frequency and outputs a first bit numerical value; a second counter receiving the first bit numerical value, the second counter counts the first bit numerical value with an exponent n in a 2.sup.n exponential function that approximates a maximum rotational speed command value and outputs a second bit numerical value; a frequency divider receiving the second bit numerical value, and the frequency divider divides the second bit numerical value from the system frequency and outputs a counting frequency; and a third counter receiving the counting frequency, and the third counter is electrically connected to a maximum frequency generator and receives a maximum frequency generated by the maximum frequency generator, and the third counter counts the maximum frequency from the counting frequency and outputs a feedback rotational speed value.

Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.

Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.

Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.

Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.

The present invention proposes a novel integrated circuit architecture for in-memory computing matrix-vector multipliers such that the computational latency is inversely proportional to the incoming magnitude of neuron activations. The main contribution of the present invention is that the proposed circuit is self-aware of the computational latency. At the end of the generated data pulses in which the number of pulses is proportional to the magnitude of incoming neuron activations, the circuit generates an end-of-computation flag such that the computing circuit can shorten the processing time of matrix-vector multiplications. The present invention can be integrated with any kind of analogue readout circuit, and the proposed circuit can be integrated with any kind of memory elements.