METHOD FOR END-OF-COMPUTATION FLAG GENERATION IN A PULSE GENERATION CIRCUIT FOR AN IN-MEMORY COMPUTING SYSTEM

Abstract

The present invention proposes a novel integrated circuit architecture for in-memory computing matrix-vector multipliers such that the computational latency is inversely proportional to the incoming magnitude of neuron activations. The main contribution of the present invention is that the proposed circuit is self-aware of the computational latency. At the end of the generated data pulses in which the number of pulses is proportional to the magnitude of incoming neuron activations, the circuit generates an end-of-computation flag such that the computing circuit can shorten the processing time of matrix-vector multiplications. The present invention can be integrated with any kind of analogue readout circuit, and the proposed circuit can be integrated with any kind of memory elements.

Claims

1. A method of computing for an in-memory computing system, the method comprising: a set of in-memory computing counters of an in-memory computing driver receiving a set of input neuron data sets through a set of input data lines; the in-memory computing driver setting an end-of-computation signal to a first end-of-computation signal value once an in-memory computing clock signal changes from a first signal value to a second signal value; the set of in-memory computing counters registering the set of input neuron data sets, a respective in-memory computing counter registering a respective input neuron data set received through a respective input data line during a respective time window; the set of in-memory computing counters initialising a set of internal counters with the set of input neuron data sets, a respective internal counter being initialised with the respective input neuron data set; setting the value of a respective flag signal of the respective in-memory computing counter to a first flag value if the value of the respective internal counter deviates from a first counter value, and increasing or decreasing the value of the respective internal counter during an adjustment cycle until the value of the respective internal counter equals the first counter value, and generating a respective set of signal pulses during the adjustment cycle to be fed to a memory array, the number of signal pulses generated during the adjustment cycle by the respective in-memory computing counter being proportional to the magnitude of the respective input neuron data set received by the respective in-memory computing counter during the respective time window; setting the value of the respective flag signal of the respective in-memory computing counter to a second flag value if the value of the respective internal counter equals the first counter value; and the in-memory computing driver setting the end-of-computation signal to a second end-of-computation signal value if the values of the flag signals of all the in-memory computing counters of the in-memory computing driver equal the second flag value.

2. The method according to claim 1, wherein a signal pulse is generated every time the value of the respective internal counter is increased or decreased.

3. The method according to claim 1, wherein the first counter value equals a signal low value, the first flag value equals a signal high value, the second flag value is a signal low value, and wherein the internal counters operate as down-counters decreasing the value of the internal counters by one at a frequency of a clock signal if the value of the respective internal counter is decreased during the adjustment cycle.

4. The method according to claim 1, wherein the first end-of-computation signal value is a signal high value, and the second end-of-computation signal value is a signal low value, and/or the end-of-computation signal is set to the first end-of-computation signal value as soon as the in-memory computing clock signal changes from a signal low value to a signal high value, or vice versa, and the end-of-computation signal is set to the second end-of-computation signal value if the values of the flag signals of all the in-memory computing counters of the in-memory computing driver equal the second flag value but only upon the in-memory computing clock signal changing from a signal low value to a signal high value, or vice versa.

5. The method according to claim 1, wherein the set of internal counters are initialised after a given delay from the registration of the set of input neuron data sets.

6. The method according to claim 1, wherein the change of the end-of-computation signal to the first end-of-computation signal value is indicative of a beginning of a signal computation cycle, and the change of the end-of-computation signal to the second end-of-computation signal value is indicative of an end-of-the signal computation cycle.

7. The method according to claim 1, wherein the method further comprises the step of feeding the end-of-computation signal to a memory array.

8. The method according to claim 1, wherein the end-of-computation signal is generated by an end-of-computation circuit comprising an arrangement of logic OR gates such that the second end-of-computation signal value is obtained as soon as the in-memory computing clock signal changes from the second signal value to the first signal value, and the values of the flag signals of all the in-memory computing counters of the in-memory computing driver equal the second flag value.

9. The method according to claim 1, wherein the respective in-memory counter comprises a respective input register for registering the respective input neuron data set, the respective internal counter, a respective reset operator for the respective internal counter and configured to receive a latch signal and the respective input neuron data set as an input data set, a respective pulse generator for generating the latch signal, and a respective flag controller for generating the respective flag signal and the respective set of signal pulses.

10. The method according to claim 9, wherein the respective internal counter comprises an individual flip-flop circuit for each bit position of the respective input neuron data set such that a respective individual flip-flop circuit is arranged to output a single bit value of the respective flip-flop circuit.

11. The method according to claim 10, wherein the respective flag controller comprises an arrangement of logic gates and is configured to receive as inputs the single bit values of the respective flip-flop circuit or their inverted values and output the respective flag signal, the respective set of signal pulses, and a clock signal to be fed to the respective internal counter.

12. The method according to claim 9, wherein the respective reset operator comprises an individual multiplexer circuit for each bit position of the respective input neuron data set to feed an individual bit to a respective individual flip-flop circuit of the counter.

13. The method according to claim 1, wherein the duty cycle of the in-memory computing clock signal is greater than 50%.

14. A computer program product comprising instructions for implementing the steps of the method according to claim 1 when loaded and run on an electronic device.

15. A computing device for an in-memory computing memory, the computing device comprising a set of in-memory computing counters, the computing device being configured to perform operations comprising: receive by the set of in-memory computing counters a set of input neuron data sets through a set of input data lines; set an end-of-computation signal to a first end-of-computation signal value once an in-memory computing clock signal changes from a first signal value to a second signal value; register by the set of in-memory computing counters the set of input neuron data sets, a respective in-memory computing counter registering a respective input neuron data set received through a respective input data line during a respective time window; initialise by the set of in-memory computing counters a set of internal counters with the set of input neuron data sets, a respective internal counter being initialised with the respective input neuron data set; set the value of a respective flag signal of the respective in-memory computing counter to a first flag value if the value of the respective internal counter deviates from a first counter value, and increasing or decreasing the value of the respective internal counter during an adjustment cycle until the value of the respective internal counter equals the first counter value, and generating a respective set of signal pulses during the adjustment cycle to be fed to a memory array, the number of signal pulses generated during the adjustment cycle by the respective in-memory computing counter being proportional to the magnitude of the respective input neuron data set received by the respective in-memory computing counter during the respective time window; set the value of the respective flag signal of the respective in-memory computing counter to a second flag value if the value of the respective internal counter equals the first counter value; and set the end-of-computation signal to a second end-of-computation signal value if the values of the flag signals of all the in-memory computing counters of the in-memory computing driver equal the second flag value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Other features and advantages of the invention will become apparent from the following description of a non-limiting example embodiment, with reference to the appended drawings, in which:

[0011] FIG. 1 schematically illustrates an overview of an in-memory computing matrix-vector multiplier according to the present invention, and where a new pulse-generation method according to the present invention may be implemented;

[0012] FIG. 2 schematically illustrates an overview of an end-of-computation (EOC) generation circuit, implemented within the in-memory computing driver as shown in FIG. 1;

[0013] FIG. 3 schematically illustrates an IMC counter, as shown in FIG. 2;

[0014] FIG. 4 is a flow chart describing the operations carried out in the circuits of FIGS. 2 and 3;

[0015] FIG. 5 describes an optional duty-cycle-controlled clock sprinting scheme;

[0016] FIG. 6 schematically illustrates an example circuit configured to adjust the duty cycle; and

[0017] FIG. 7 is a diagram showing the comparison of the computation latency according to the method of the present invention when compared to a baseline design referring to the worst-case synchronised pulse-count modulation method, as used in U.S. Pat. No. 11,322,195B2.

DETAILED DESCRIPTION OF AN EMBODIMENT OF THE INVENTION

[0018] An embodiment of the present invention will now be described in detail with reference to the attached figures. Identical or corresponding functional and structural elements which appear in different drawings are assigned the same reference signs. It is to be noted that the use of words first and second may not imply any kind of particular order or hierarchy unless such order or hierarchy is explicitly or implicitly made clear in the context. In the present description, signal value 0 represents a signal low value, or logic zero, while signal value 1 represents a signal high value, or logic high. In other words, signal value 0 may be considered to be a first or second signal value, while signal value 1 may be considered to be a second or first signal value. Similarly, flag value 0 may be considered to be a first flag value or a second flag value, while flag value 1 may be considered to be a second flag value or a first flag value. Furthermore, counter value 0 is in the following also referred to as a first counter value.

[0019] FIG. 1 shows an overview of the proposed in-memory computing system 1, which in this example is a matrix-vector multiplier, and where the proposed pulse-generation method may be implemented. The system comprises an in-memory computing driver (IMC driver) 3, a clock generator 4, and a memory array 5. The clock generator is configured to receive a first clock signal, which is a master clock signal f.sub.Master, such that the clock generator is configured to generate a second clock signal f.sub.IMC also referred to as an in-memory computing clock signal, which is a local clock signal, from the master clock signal. The second clock signal is then subsequently fed to the IMC driver 3. The k+1-bit input neuron data from input neurons (X.sub.0, 1, . . . , N) are converted by the IMC driver into pulses or pulsed signals, which are configured to be fed into the memory array 5. The number of pulses represents the magnitude of the input data and is thus in this case directly proportional to the magnitude of the input data. It is to be noted that the notations [k:0] and [m:0] in FIG. 1 mean that the input data of the IMC driver 3 of a given input neuron X are represented in k+1 bits, and the output data of a given memory cell are represented in m+1 bits, respectively. For instance, if k=2, then the input data of the IMC driver 3 of a given input neuron X are represented in three bits, having bit positions 1, 2, and 3. In this case, the three bit values can represent magnitude values comprised between 0 and 7 ([0:7]). The memory array 5 is in this example a compute-in-memory RAM, such as SRAM, DRAM, ReRAM, PCM, MRAM, or memory FeRAM.

[0020] Time windows T.sub.1, T.sub.2, etc. define a computational or counting cycle for the memory array 5. According to the present invention, the length of these time windows is dynamically adjusted based on the maximum number of pulses transferred in a given time window. According to prior art solutions, the length of these time windows is fixed. For instance, the length of these time windows in the solution disclosed in U.S. Pat. No. 11,322,195B2 is 7. According to the present invention, for example: [0021] In the time window T.sub.1, X.sub.0=4 outputs 4 pulses, X.sub.1=0 outputs no pulses, X.sub.2=1 outputs 1 pulse, X.sub.3=2 outputs 2 pulses, and X.sub.N=1 outputs 1 pulse. [0022] In the time window T.sub.2, X.sub.0=0 outputs no pulses, X.sub.1=2 outputs 2 pulses, X.sub.2=1 outputs 1 pulse, X.sub.3=0 outputs no pulses, and X.sub.N=1 outputs 1 pulse.

[0023] Determining the window duration (T.sub.1, T.sub.2, . . . ), which is the period of the end-of-computation (EOC) signal, is the main novelty of the present invention. As described in FIG. 2, the proposed IMC driver 3 generates the EOC signal according to the maximum magnitude of input neurons (X.sub.0, 1, . . . , N). The EOC signal may be considered to be a clock signal, and in particular in this case a third clock signal. For example: [0024] In the time window T.sub.1, X.sub.0=4 is the greatest magnitude among all the input neurons (X.sub.0, 1, . . . , N). The EOC signal is synchronised to the last pulse of X.sub.0=4. Meanwhile, the other input neurons stay idle. [0025] In the time window T.sub.2, X.sub.1=2 is the largest magnitude among all the input neurons (X.sub.0, 1, . . . , N). The EOC signal is synchronised to the last pulse of X.sub.1=2. Meanwhile, the other input neurons stay idle.

[0026] As is shown in FIG. 1, the clock f.sub.IMC is applied to the IMC driver 3. f.sub.IMC is generated by the clock generator 4 whose clock port is driven by f.sub.master. The generated pulses are applied to the memory array 5 (which in this case is a compute-in-memory matrix). The results of matrix-vector multiplication are available with m+1-bit output neurons (Y.sub.0, 1, . . . , L).

[0027] FIG. 2 shows an overview of the EOC signal generation circuit 7 comprising in this case a set of logic OR gates 8 and implemented within the IMC driver 3 as shown in FIG. 1. Each k+1-bit input neuron data are applied row-wise to a respective IMC counter 9 through input data or bit lines (one input bit line per IMC counter 9). A counter flag signal FLG.sub.CNT(N) and a word line enable signal EN.sub.WL(N) are the outputs of the IMC counters 9 (illustrated in more detail in FIG. 3). The EN.sub.WL(N) signals or IMC driver output signals represent the number of pulses that are converted from the input neurons (X.sub.0, 1, . . . , N), as shown in FIG. 1. EN.sub.WL(N) signals are directed to the memory array side (shown in FIG. 1) while FLG.sub.CNT(N) signals are directed internally within the IMC driver side. In this example, the falling edge of a FLG.sub.CNT(N) signal represents the condition that the N.sup.th IMC counter 9 reaches 0, where the IMC counter is a down-counter, counting from the maximum or current value to zero value. In this example, the FLG.sub.CNT(N) signal stays 1 if the N.sup.th IMC counter is still counting.

[0028] In this example, the EOC signal goes to the 0 state, when all the N+1 IMC counters reach the 0 state, and it stays in the 0 state until the next rising edge of f.sub.IMC. The EOC signal is generated by combining all N+1 FLG.sub.CNT(N) signals and the f.sub.IMC signal by OR gating. The EOC signal is shared between all the N+1 IMC counters 9 ensuring all the N+1 IMC counters are synchronised. If any IMC counter is still down counting, such that the falling edge of the FLG.sub.CNT(N) signal is not generated (at least one FLG.sub.CNT(N)=1), the output of O.sub.1 gate as shown in FIG. 2 stays 1 by OR gating. When the output of O.sub.1 gate stays 1, the value of the EOC signal is in this example always 1. This ensures that all flip-flops in the IMC counters as shown in FIG. 3 except for down-counters within the N+1 IMC counters stay inactive since no rising edges of the EOC signal are generated. Flip-flops are digital circuits used to implement registers and counters and are characterised in FIG. 3 by parameters D, RS, Q, and Q. Furthermore, the symbol > indicates that the device is edge-triggered. If all the N+1 IMC counters 9 finished the down-counting and thus all of them generated a falling edge (all FLG.sub.CNT(N)=0), the output of O.sub.1 gate goes to 0 with a falling edge of f.sub.IMC. When the output of O.sub.1 gate goes to 0, the EOC signal goes to 0 with a falling edge of f.sub.IMC and stays in that state until the next rising edge of f.sub.IMC. At this moment, the EOC signal generates a rising edge. If all the N+1 IMC counters 9 receive 0s from their respective input neuron (X.sub.0, 1, . . . , N), the output of O.sub.1 gate stays 0 and thus the EOC signal is nothing but the buffered f.sub.IMC signal.

[0029] FIG. 3 shows a schematic diagram of the IMC counter 9. FIG. 3 shows an example that uses a three-bit input neuron (X.sub.0, 1, . . . , N), but the input bit precision can be arbitrarily chosen. Since this example uses a three-bit input neuron case, register (REG), counter (CNT), and multiplexers are drawn accordingly with three bits. The respective IMC counter 9 comprises: 1) an input register 15 that outputs REG[2:0], 2) an internal counter 16, which in this example is a down-counter, that outputs CNT[2:0], 3) a reset operator 17 with multiplexers 18 that receives REG[2:0] as well as a latch signal LAT.sub.CNT as inputs, 4) a pulse generator 19 that receives the EOC signal as input and outputs LAT.sub.CNT, and 5) a flag controller 20 that outputs EN.sub.WL(N) and FLG.sub.CNT(N) signals, as well as a CKC signal, which is a fourth clock signal. The counter 16 comprises an individual flip-flop circuit 23 for each bit position of the respective input neuron data set such that a respective individual flip-flop circuit is arranged to output a single bit value of the respective flip-flop circuit. The flag controller 20 comprises an arrangement of logic gates and is configured to receive as inputs the single bit values of the respective flip-flop circuit 23 or their inverted values and output the flag signal, the signal pulses, and a clock signal to be fed to the counter 16. As is shown in FIG. 3, the flag controller 20 in this example comprises a logic NAND gate N.sub.1, a first AND gate A.sub.1, and a second AND gate A.sub.2. Inverted counter output data sequence is configured to be fed into the NAND gate N.sub.1, whose output is inverted. The first AND gate A.sub.1 is configured to output the CKC signal, which is configured to be fed into the counter 16. The reset operator 17 comprises an individual multiplexer circuit for each bit position of the respective input neuron data set to feed an individual bit to a respective individual flip-flop circuit 23 of the counter 16.

[0030] The input neurons (X.sub.0, 1, . . . , N) are in this example registered with REG[2:0] at the rising edge of the EOC signal. After a short delay, LAT.sub.CNT, which is a short pulse, is generated. LAT.sub.CNT is used to initialise the counter 16 according to the input neuron values.

[0031] If X[2:0] is non-zero such that REG[2:0] is also non-zero, then at least one bit of CNT[2:0] will be initialised as 1 thereby making the output of the NAND gate N.sub.1 1, which is FLG.sub.CNT. Then the first AND gate A.sub.1 becomes a buffer of negative or inverted f.sub.IMC signal to CKC, which is a counter-clock. In this case, the CKC signal keeps down-counting the initialised flip-flops 23 until CNT[2:0] reaches the 0 state. Since FLG.sub.CNT is 1, EN.sub.WL is outputting pulses while the counter is down-counting. If the CNT[2:0] reaches 0, the output of the NAND gate N.sub.1 (FLG.sub.CNT) becomes 0 and thus both CKC and EN.sub.WL are gated, i.e. kept to 0, ensuring the counter is inactive.

[0032] For example, if X[2:0]=3, then: [0033] REG[2:0] is registered as 011 and thus the counter 16 is initialised as 011 at the LAT.sub.CNT pulse. [0034] The FLG.sub.CNT is 1 and thus every falling edge of f.sub.IMC signal activates the counter 16 to count down. [0035] Since it requires three pulses to count CNT[2:0] down to 0, EN.sub.WL outputs 3 pulses which are synchronised with f.sub.IMC. [0036] When the counter 16 reaches 0, the FLG.sub.CNT becomes 0 and EN.sub.WL generates no pulses. [0037] When the rising edge of the EOC signal comes in, the same operating cycles begin. [0038] The magnitude of X[2:0] determines how many cycles are required to make FLG.sub.CNT signal to 0, and thus the EOC signal to 0, seamlessly realising the magnitude-aware computation latency.

[0039] For example, if X[2:0]=0, then: [0040] REG[2:0] is registered as 000 and thus the counter 16 is initialised as 000 at the LAT.sub.CNT pulse. [0041] The FLG.sub.CNT signal stays 0 and thus EN.sub.WL signal generates no pulses, seamlessly supporting the input sparsity management without requiring any additional circuitry. [0042] When the rising edge of the EOC signal comes in, the same operating cycles begin.

[0043] The flow chart of FIG. 4 summarises the operations described in connection with FIGS. 2 and 3. Thus, in this case, the method described in the flow chart of FIG. 4 is carried out by the in-memory computing driver 3. At step 41, the IMC counters 9 receive a set of input neuron data sets such that a respective IMC counter 9 receives a respective input neuron data set or sequence, which in this case is a bit sequence. At step 42, it is determined whether or not a rising edge (or a falling edge in another implementation) of the f.sub.IMC signal is detected. In the affirmative, the EOC signal is set to 1 at step 43. At step 44, the respective register 15 registers or stores the respective input data sequence X[k:0]. At step 45, the respective counter CNT[k:0] 16 is initialised with X[k:0]. At step 46, it is determined whether or not the respective counter value equals a given value, which in this case is value 0. If the respective counter value is not yet 0, then at step 47 FLG.sub.CNT signal is set to 1. At step 48, the CKC signal is used to down-count the counter CNT[k:0] 16. In other words, at this step, a given value, in this case value 1, is subtracted from (or added to if the counter 16 is configured as an up-counter) the current counter value at a given frequency defined by the signal CKC. At step 49, the EN.sub.WL signal is set to f.sub.IMC. In other words, the waveform and/or frequency of EN.sub.WL is set to follow the frequency and/or waveform of f.sub.IMC. Steps 48 and 49 may be implemented substantially mutually simultaneously. From steps 48 and 49 the process continues at step 46, where it is again determined whether or not the counter value is 0. Steps 47, 48, and 49 form an adjustment cycle during which the value of the counter CNT[k:0] 16 is updated, i.e., in this example the value of the counter is decreased by one at every adjustment cycle. If at step 46 it is determined that the counter value equals 0, then the process continues at step 50, where in this example the respective FLG.sub.CNT signal is set to 0. Then at step 51, in this example, both the CKC signal and the EN.sub.WL signal are set to 0. It is to be noted that steps 43 to 51 are carried out for each IMC counter 9, in this case in parallel, although in another implementation, at step 43, the EOC signal may be centrally set to 1 for all of the IMC counters 9, or at least for more than one IMC counter. The process then continues at step 52, where it is determined whether or not all the flag counter values equal 0. In the affirmative, at step 53, the EOC signal is in this example set to 0 at the next falling edge of f.sub.IMC. If this is not the case, then the EOC signal remains at level 1 (step 54). From step 54 the process continues to step 52. The change of the EOC signal from state 1 to state 0 in this case is indicative of the end of the signal computation cycle. In other words, change of the signal state of the EOC signal serves as an indication that all data pulses have been received across a plurality of data lines within a given computation cycle or time window, leading to magnitude-proportional latency. From step 53 the process continues to step 42, where the next cycle begins. The method advantageously also comprises the step of feeding the EOC signal to the memory array 5. As soon as the EOC signal is generated, it may be continuously fed to the memory array 5.

[0044] FIGS. 5 and 6 describe the optional duty-cycle-controlled clock sprinting scheme. FIG. 5, where OUT.sub.IMC corresponds to Y[m:0] in FIG. 1, illustrates the principle and FIG. 6 shows a schematic circuit configuration for implementing the clock sprinting scheme. If the input neuron data from the input neurons (X.sub.0, 1, . . . , N) are represented with the pulse-count modulation method, with a 50% duty cycle, EN.sub.WL(N) data also maintain a 50% duty cycle. In this condition, the in-memory computing circuit, i.e., the IMC driver 3, stays idle for 50% of the time during EN.sub.WL(N) signal's 0 state. According to this variant of the invention, the duty cycle of the in-memory computing clock f.sub.IMC is set to greater than 50%, for example greater than 60% or 70%, to hide the idle time. In this figure, a duty cycle of 80% is adopted as an example. However, an even higher percentage of the duty cycle can be used by adding and rearranging flip-flops 30, which in this configuration are arranged in two rings in a series configuration. nRST shown in FIG. 6 is a reset signal for the flip-flops 30. With an 80% duty-cycled IMC clock and the same pulse width, this variant of the present invention achieves 37.5% computation latency improvement compared to the baseline 50% duty-cycle method.

[0045] FIG. 7 shows the comparison of the computation latency of the present invention. Baseline design refers to the worst-case synchronised pulse-count modulation method, as used in U.S. Pat. No. 11,322,195B2. For example, with a three-bit (000.sub.2 to 111.sub.2) input neuron, the possible set of the number of pulses is 0 to 7. The baseline design synchronises the computation latency to the worst case, 7 pulses, such that it is not input-magnitude-aware. On the other hand, the proposed magnitude-aware end-of-computation method adaptively scales the in-memory computing latency achieving up to 7 smaller latency than the baseline design case. Furthermore, by applying the magnitude-aware method and clock sprinting method altogether, the present invention can achieve another 37.5% latency improvement.

[0046] To summarise the above teachings, one aspect of the present invention proposes a novel integrated circuit architecture for in-memory computing matrix-vector multipliers such that the computational latency is inversely proportional to the incoming magnitude of neuron activations. The main contribution of the present invention is that the proposed circuit is self-aware of the computational latency. At the end of the generated data pulses in which the number of pulses is proportional to the magnitude of incoming neuron activations, the circuit generates an end-of-computation flag such that the computing circuit can shorten the processing time of matrix-vector multiplications. The present invention can be integrated with any kind of analogue readout circuit, such as oscillator-based analog-to-digital converter (ADC), or successive approximation register (SAR) ADC. The proposed circuit can be integrated with any kind of memory elements, such as static random-access memory (SRAM), memristors, etc.

[0047] It is to be noted the above-described method may be modified in many ways. For instance, instead of operating as a down-counter, the counter 16 may operate as an up-counter counting up to a given threshold value. In this case, at step 48 the CKC signal would be used to up-count the counter until the given threshold value is reached. Furthermore, instead of an action being triggered at a rising or falling edge, the action could be triggered at a falling or rising edge, respectively. Moreover, a different arrangement of logic gates may be used depending how the signals are arranged.

[0048] The method steps described above may be carried out by suitable circuits or circuitry when the process is implemented in hardware or using hardware for individual steps. However, the method or at least some of the method steps may also or instead be implemented in software. Thus, at least some of the method steps can be considered as computer-implemented steps. The terms circuits and circuitry refer to physical electronic components or modules (e.g., hardware), and any software and/or firmware (code) that may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. The circuits may thus be operable (i.e., configured) to carry out or they comprise means for carrying out the required method steps as described above.

[0049] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive, the invention being not limited to the disclosed embodiment. Other embodiments and variants are understood, and can be achieved by those skilled in the art when carrying out the claimed invention, based on a study of the drawings, the disclosure and the appended claims. Further embodiments may be obtained by combining any of the teachings above.

[0050] In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. The mere fact that different features are recited in mutually different dependent claims does not indicate that a combination of these features cannot be advantageously used. Any reference signs in the claims should not be construed as limiting the scope of the invention.