Patent classifications
G06F7/72
Elliptic curve random number generation
An elliptic curve random number generator avoids escrow keys by choosing a point Q on the elliptic curve as verifiably random. An arbitrary string is chosen and a hash of that string computed. The hash is then converted to a field element of the desired field, the field element regarded as the x-coordinate of a point Q on the elliptic curve and the x-coordinate is tested for validity on the desired elliptic curve. If valid, the x-coordinate is decompressed to the point Q, wherein the choice of which is the two points is also derived from the hash value. Intentional use of escrow keys can provide for back up functionality. The relationship between P and Q is used as an escrow key and stored by for a security domain. The administrator logs the output of the generator to reconstruct the random number with the escrow key.
Systolic parallel Galois hash computing device
A computing device (e.g., an FPGA or integrated circuit) processes an incoming packet comprising data to compute a Galois hash. The computing device includes a plurality of circuits, each circuit providing a respective result used to determine the Galois hash, and each circuit including: a first multiplier configured to receive a portion of the data; a first exclusive-OR gate configured to receive an output of the first multiplier as a first input, and to provide the respective result; and a second multiplier configured to receive an output of the first exclusive-OR gate, wherein the first exclusive-OR gate is further configured to receive an output of the second multiplier as a second input. In one embodiment, the computing device further comprises a second exclusive-OR gate configured to output the Galois hash, wherein each respective result is provided as an input to the second exclusive-OR gate.
Bit decomposition secure computation apparatus, bit combining secure computation apparatus, method and program
The present invention provides a bit decomposition secure computation system comprising: a share value storage apparatus to store share values obtained by applying (2, 3) type RSS using modulo of power of 2 arithmetic; a decomposed share value storage apparatus to store a sequence of share values obtained by applying (2, 3) type RSS using modulo 2 arithmetic; and a bit decomposition secure computation apparatus that, with respect to sharing of a value w, r1, r2, and r3 satisfying w=r1+r2+r3 mod 2{circumflex over ( )}n, where {circumflex over ( )} is a power operator and n is a preset positive integer, being used as share information by the (2, 3) type RSS stored in the share value storage apparatus, includes: an addition sharing unit that sums two values out of r1, r2 and r3 by modulo 2{circumflex over ( )}n, generates and distributes a share value of the (2, 3) type RSS with respect to the sum; and a full adder secure computation unit that executes addition processing of the value generated by the addition sharing unit and a value not used by the addition sharing unit, for each digit, by using secure computation of a full adder, and stores the result in the decomposed share value storage apparatus.
Measurement based uncomputation for quantum circuit optimization
Methods and apparatus for optimizing a quantum circuit. In one aspect, a method includes identifying one or more sequences of operations in the quantum circuit that un-compute respective qubits on which the quantum circuit operates; generating an adjusted quantum circuit, comprising, for each identified sequence of operations in the quantum circuit, replacing the sequence of operations with an X basis measurement and a classically-controlled phase correction operation, wherein a result of the X basis measurement acts as a control for the classically-controlled correction phase operation; and executing the adjusted quantum circuit.
Measurement based uncomputation for quantum circuit optimization
Methods and apparatus for optimizing a quantum circuit. In one aspect, a method includes identifying one or more sequences of operations in the quantum circuit that un-compute respective qubits on which the quantum circuit operates; generating an adjusted quantum circuit, comprising, for each identified sequence of operations in the quantum circuit, replacing the sequence of operations with an X basis measurement and a classically-controlled phase correction operation, wherein a result of the X basis measurement acts as a control for the classically-controlled correction phase operation; and executing the adjusted quantum circuit.
System and method of performing discrete frequency transform for receivers using single-bit analog to digital converters
A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.
System and method of performing discrete frequency transform for receivers using single-bit analog to digital converters
A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.
PERSONNEL INSPECTION WITH THREAT DETECTION AND DISCRIMINATION
A method includes receiving, from a plurality of magnetic field receivers including magnetic sensors, data characterizing samples obtained by the plurality of magnetic field receivers, the samples of a combination of a first magnetic field and a second magnetic field resulting from interaction of the first magnetic field and an object; determining, using the received data, a polarizability index of the object, the polarizability index characterizing a magnetic polarizability property of the object; classifying, using the determined polarizability index, the object as threat or non-threat; and providing the classification. Related apparatus, systems, techniques, and articles are also described.
PERSONNEL INSPECTION WITH THREAT DETECTION AND DISCRIMINATION
A method includes receiving, from a plurality of magnetic field receivers including magnetic sensors, data characterizing samples obtained by the plurality of magnetic field receivers, the samples of a combination of a first magnetic field and a second magnetic field resulting from interaction of the first magnetic field and an object; determining, using the received data, a polarizability index of the object, the polarizability index characterizing a magnetic polarizability property of the object; classifying, using the determined polarizability index, the object as threat or non-threat; and providing the classification. Related apparatus, systems, techniques, and articles are also described.
PARALLEL FINITE FIELD MULTIPLICATION DEVICE
A parallel finite field multiplication device is disclosed. The device comprises M cascaded logic processing modules, each of which comprises four input ends and two output ends for carrying out different finite multiplication in different length. The device is calculated step by step through M cascaded logic processing modules according to the number of cascaded logic processing modules. In this device, M cascaded logic processing modules may be used, according to different numbers of the cascaded logic processing modules, in finite field multiplication of different lengths, without needing to carry out polynomial multiplication.