Disclosed are various embodiments for improving the resiliency and performance for clustered memory. A computing device can mark a page of the memory as being reclaimed. The computing device can then set the page of the memory as read-only. Next, the computing device can submit a write request for the contents of the page to individual ones of a plurality of memory hosts. Subsequently, the computing device can receive individual confirmations of a successful write of the page from the individual ones of the plurality of memory hosts. Then, the computing device can mark the page as free in response to receipt of the individual confirmations of the successful write from the individual ones of the plurality of memory hosts.

An indication is received. The indication is of an address in a first page in virtual memory used by an application with a static memory corruption. A loadable kernel module will monitor the address. Access to the first page in virtual memory is changed from read/write access to read only access. A second page in virtual memory is created with read/write access. Whether a page fault occurs on the first page in virtual memory during the execution of the application with the static memory corruption is determined.

A method of site isolation protection includes the following steps. A set of clustered engines including a first engine at a first site and a second engine at a second site is provided. A Fiber Channel (FC) connection and an Ethernet connection between the first and the second sites are provided. Whether an Ethernet Heartbeat (EH) from one of the first engine and the second engine through the Ethernet connection exists is detected when the FC connection fails. One of the first engine and the second engine is shut down when the EH exists. Furthermore, a quorum service at a client site is provided in different IP domain to further protect site isolation from happening, while the FC connection and Ethernet Heartbeat connection failed at the same time.

Provided are a computer program product, system, and method for after swapping from a first storage to a second storage, mirroring data from the second storage to the first storage for data in the first storage that experienced data errors. A swap operation redirects host Input/Output (I/O) requests to data from the first server to the second server in response to a health condition at the first server. A determination is made of data errors with respect to data in the first storage that experienced data errors. The second server is instructed to mirror data in the second storage to the first server including data for the data in the first storage that experienced the data errors to store in the first storage in response to determining that the first server is available for the data mirroring operations.

According to the present invention, a process that requires for creating a backup at a designated time point is executed by sharing among a plurality of storage control apparatuses. An intermediate storage apparatus 2 reads journal data and a JNCB from a primary storage apparatus 1, and stores the journal data and the JNCB in an intermediate journal volume 28. A secondary storage apparatus 3 reads the journal data and the JNCB from the intermediate storage apparatus 2, and stores the journal data and the JNCB in a secondary journal volume 38. After the secondary storage apparatus 3 having a designated generation restores the journal data up to a designated time point into a secondary data volume 37, the secondary storage apparatus 3 splits a copy pair. Another secondary storage apparatus 3 executes a regular restoring process.

According to the present invention, a process that requires for creating a backup at a designated time point is executed by sharing among a plurality of storage control apparatuses. An intermediate storage apparatus 2 reads journal data and a JNCB from a primary storage apparatus 1, and stores the journal data and the JNCB in an intermediate journal volume 28. A secondary storage apparatus 3 reads the journal data and the JNCB from the intermediate storage apparatus 2, and stores the journal data and the JNCB in a secondary journal volume 38. After the secondary storage apparatus 3 having a designated generation restores the journal data up to a designated time point into a secondary data volume 37, the secondary storage apparatus 3 splits a copy pair. Another secondary storage apparatus 3 executes a regular restoring process.

A system, method and apparatus to provide data recovery capabilities during an emergency power failure event. A non-volatile storage system is provided to be coupled with a host computer system. The non-volatile storage system includes an embedded non-volatile memory array for persistently storing data and an embedded volatile memory array for temporarily storing the data before committing the data to the non-volatile memory array. The non-volatile storage system provides a normal operating data path transferring data from the volatile memory array to the non-volatile memory array during normal operating condition. The normal operating data path includes data processing blocks. The non-volatile storage system also provides an emergency data path for transferring data from the volatile memory array to the non-volatile memory array during an emergency power loss condition. The emergency data path excludes the data processing blocks.

A frequency converter has a control unit. The control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, wherein data are transmitted via the serial control unit interface depending on the control unit clock pulse, and a control unit processor which is designed to define at least one control parameter depending on at least one actual value. The frequency converter furthermore has a power unit which has a data connection to the control unit and has: a number of power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface which is connectable to the control unit interface in order to set up a data connection, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which is designed to adjust the power unit clock pulse depending on signals which are received by the power unit on the power unit interface, a power unit processor which is designed to control the power semiconductors depending on the control parameter and the power unit clock pulse, and at least one sensor unit which is designed to determine the at least one actual value, wherein the control unit is designed to transmit the at least one control parameter via the control unit interface to the power unit, and wherein the power unit is designed to transmit the at least one actual value via the power unit interface to the control unit.

The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.

A receiver device includes detection logic, an error counter, and an interrupt logic. The detection logic is to receive a first set of data frames and detect one or more frame errors in the first set of data frames. The error counter is to store a number of the one or more frame errors detected in the first set of data frames. The interrupt logic can be coupled to the error counter. The interrupt logic is to specify a period and compare the number of the one or more frame errors with a threshold number of frame errors during the period, where the interrupt logic is to indicate an interrupt responsive to the number of the one or more frame errors detected within the period satisfying the threshold number of frame errors.