Secure data transmission between an input device and both industrial controllers in a high-availability system utilizes a secure connection established between the primary industrial controller and the input device. Data required to establish the secure connection is stored on the primary controller as part of the connection data corresponding to the secure connection. The input device transmits data to the primary controller over the secure connection according to the desired level of security. The primary controller transmits the connection data defining the secure connection to the secondary controller. If a failure occurs in the primary controller, the secondary controller establishes a connection to the input device using the connection data for the secure connection, such that the secondary controller may assume responsibility for the controller end of the secure connection. The primary controller transmits the input signals to the secondary controller via the dedicated connection between controllers.

A process control system includes first type and second type controllers having different hardware architectures coupled together by a redundancy network for providing a controller pool. Primary application modules (AMs) are coupled to the controller platforms by a plant-wide network. The controller platforms are coupled by an input/output (I/O) mesh network to I/O devices to provide an I/O pool coupled to field devices coupled to processing equipment. A translating device translates states and values from one of the primary AMs running on a first type controller to generate a backup AM having an instruction set compatible with the second type controller. A controller application module orchestrator (CAMO) extends synchronization to the second type controller, makes the backup AM available to the second type controller, and then switches to utilize the second type controller as an active controller running the process.

A method for protecting a reconfigurable digital integrated circuit includes multiple parallel processing channels each comprising an instance of a functional logic block and an error detection unit, the method comprising the successive steps of: activating the error detection unit in order to detect an error in at least one processing channel, executing the data replay mechanism, and then activating the error detection unit in order to detect an error in at least one processing channel, if an error is detected again, executing a self-test on each processing channel, for each processing channel, if the self-test does not detect any error, executing the data replay mechanism for this processing channel, if the self-test detects an error, reconfiguring that part of the configuration memory associated with this processing channel.

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Fault detection devices, systems, and methods are provided which implement identical processors. A first processor is configured to receive a first measurement, execute a first firmware based on the first measurement, and output a first result of the executed first firmware. A second processor is configured to receive a second measurement, execute a second firmware based on the second measurement, and output a second result of the executed second firmware. The first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin.

A method for storing a key-value pair can include dividing the key-value pair into a first data record and a second data record. The first data record can include a key associated with the key-value pair. The second data record can include a portion of a value associated with the key-value pair. The second data record can be stored in a secondary data store based on a size of the second data record exceeding a threshold value. The first data record can be stored in an in-memory key-value store based on a size of the first data record not exceeding the threshold value. The first data record can include a reference to the second data record in the secondary data store. A query requiring the key-value pair can be executed by retrieving the first data record from the in-memory key-value store. Related systems and articles of manufacture are also provided.

A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.