A workgroup-computing-entity-based fail-safe/evolvable hardware core structure is disclosed which includes a 3-hierarchical-level 6-workgroup-Basic-Building-Block (6-wBBB) created to supplant the node-computing-entity-based non-fail-safe/limited evolvable von-Neumann core structure of 3-hierarchical-level 3-node-BBB, (i.e., base-level IO-devices/mid-level main memory/top-level CPU) and all the first-time fail-safe workgroup systems can be subsequently generated in the second period along the workgroup-computing evolutionary timeline. Furthermore, based on the first 6-wBBB evolvable architecture, the workgroup evolutionary processes can go up to 7 generations in creating all the necessary workgroup-computing entity-based hardware core structures, so that all the real-time intelligent workgroup-computing systems can be generated in the third period along the workgroup-computing evolutionary timeline.

Embodiments of the present invention provide systems and methods for recovering a high availability storage system. The storage system includes a first layer and a second layer, each layer including a controller board, a router board, and storage elements. When a component of a layer fails, the storage system continues to function in the presence of a single failure of any component, up to two storage element failures in either layer, or a single power supply failure. While a component is down, the storage system will run in a degraded mode. The passive zone is not serving input/output requests, but is continuously updating its state in dynamic random access memory to enable failover within a short period of time using the layer that is fully operational. When the issue with the failed zone is corrected, a failback procedure brings the system back to a normal operating state.

A dispensing device for dispensing lids from a stack of nested lids, including a magazine containing a stack; a denesting unit arranged at a bottom of the magazine to detach lids from the stack bottom; and denesting rollers each of which has a lower shelf, a first upper shelf above a bottom shelf, and a second upper shelf above the first upper shelf. Some of the rollers comprise a first separator, and other denesting rollers comprise at least a second separator. The rollers are rotatable between a rest position in which the stack rests on the lower shelves; a single release position in which the first separators engage the stack to detach the last item from the stack bottom; and said rest position and a multiple release position in which the second separators engage the stack to detach at least the last two items from the stack bottom.

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

The disclosure herein describes enhancing data durability of a base component using multiple delta components. A first and second delta component are generated based on the base component becoming unavailable. A write operation targeted for the base component is routed to the first delta component and to the second delta component. Based on routing the write operation targeted for the base component to the first delta component and to the second delta component, a bit associated with a data block affected by the write operation is changed in each of the tracking bitmaps of the first and second delta components. Based on detecting the base component becoming available, one delta component of the first and second delta components is selected, and the data block affected by the routed write operation is synchronized from the selected delta component to the base component. Later, the first and second delta components are removed.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for resynchronizing data in a storage system. One of the methods includes determining that a particular disk of a capacity object of a storage system is out-of-sync and that a primary disk is unavailable; and for each segment of one or more segments of the capacity object: generating a first version of the column of the segment corresponding to the unavailable primary disk; determining whether the data integrity token in the column summary of the generated first version is valid; and in response to determining that the data integrity token is valid, resynchronizing the column of the segment corresponding to the particular disk using i) the primary columns of the segment corresponding to each available primary disk and ii) the first version of the column of the segment corresponding to the unavailable primary disk.

Aspects of the disclosure generally relate to computing devices and may be generally directed to devices, systems, methods, and/or applications for learning the operation of a computing device or software application, storing this knowledge in a knowledgebase, neural network, or other repository, and enabling autonomous operation of the computing device or software application with partial, minimal, or no user input.

A computer-implemented method according to one aspect includes determining whether an operating system of a node of a distributed computing environment is functioning correctly by sending a first management query to the node; in response to determining that the operating system of the node is not functioning correctly, determining whether the node has an active communication link by sending a second management query to ports associated with the node; and in response to determining that the node has an active communication link, resetting the active communication link for the node by sending a reset request to the ports associated with the node.

A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.