A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

A memory device includes cyclic redundancy check (CRC) circuitry configured to indicate whether an error has been detected in transmission of data from a host device to the memory device. The CRC circuitry includes a synchronous counter that is configured to synchronize a count with a system clock and to transmit the count. The CRC circuitry also includes pulse width control circuitry that is configured to receive the synchronized count from the synchronous counter and to generate pulse width controls based at least in part on the synchronized count. Furthermore, the CRC circuitry includes synchronization circuitry that is configured to receive the pulse width controls and to generate an error alert signal based at least in part on the pulse width controls.

A storage system comprises a plurality of storage devices, and is configured to establish a redundant array of independent disks (RAID) arrangement comprising a plurality of stripes, with each of the plurality of stripes comprising a plurality of blocks, the blocks being distributed across multiple ones of the storage devices. In conjunction with establishment of the RAID arrangement, the storage system is further configured, for each of the plurality of stripes, to designate multiple ones of the storage devices as respective spare devices for that stripe, and for each of the storage devices, to determine numbers of the stripes for which that storage device is designated as a spare device for respective ones of the other storage devices in each of multiple spare levels and for each of multiple failure combinations. A particular number of spare blocks is reserved for each of the storage devices using the determined numbers.

Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

A method including executing a portion of a service which is part of at least one service provided by a system including a distributed computing platform; determining object capability parameters required to perform the executing; storing information about at least one target host device; generating an announcement message reporting presence of a service type and the object capability parameters; receiving information from other announcement messages; evaluating current host device capability parameters with respect to the object capability parameters; determining when the current host device capability parameters meet a criterion; initiating a migration request message from the object for migration of the object, the object including software code and processing instructions and service function instructions, the migration to a target object host device, when the module capability parameters meet a criterion; and managing the migration of the object to the target host device.

A data duplication device (200) determines a duplication range using a data processing graph. The data processing graph indicates information of input/output data to and from a duplicate source program involved in a duplicate source system (110). The duplication range is a range of data to duplicate from the duplicate source system to a duplicate destination system (120). The data duplication device acquires duplicate data corresponding to the duplication range from the duplicate source system. The data duplication device registers the duplicate data with the duplicate destination system.

A computer system that has two or more processing engines (PE), each capable of performing one or more operations on one or more operands but one or more of the PEs performs the operations unreliably. Initial results of each operation are debiased to create a debiased result used by the system instead of the initial result. The debiased result has an expected value equal to a correct output where the correct output is the initial result the respective operation would have produced if the respective operation performed was reliable.

Techniques for splitting a disk set involve obtaining stripe shared information in a first disk set, wherein the information indicates a stripe set that shares a plurality of disks. The techniques further involve determining the number of disks to be split from the first disk set. The techniques further involve splitting the first disk set into a first portion and a second portion based on the information and the number of disks to be split, wherein the second portion and one or more newly added disks form a second disk set, and both the first disk set and the second disk set store data through Redundant Array of Independent Disks (RAID). In the case that a current disk set needs to be split due to adding one or more new disks, disks are selected using the collected information, thereby reducing data movements caused by splitting of the disk set.

A method, computer program product, and computing system for writing, from a first node to a second node, a first portion of data from a memory pool in the first node defined by, at least in part, a first pointer. One or more input/output (IO) operations may be received while writing the first portion of data to the second node. Data from the one or more IO operations may be stored within the memory pool after the first pointer.

An electronic control device includes: a diagnostic circuit unit configured to be reconfigurable so as to be used to diagnose each of a plurality of processing circuits that processes an input signal; an input data storage unit configured to temporarily store the input signal; an output data storage unit configured to temporarily store an output signal of the plurality of processing circuits; a reconfiguration control unit configured to sequentially write, to the diagnostic circuit unit as circuit configuration information, circuit information the same as that of the plurality of processing circuits; a diagnostic control unit configured to cause the diagnostic circuit unit to perform calculation using the input signal stored in the input data storage unit when the circuit configuration information is written to the diagnostic circuit unit; and a comparator configured to diagnose each of the plurality of processing circuits by comparing output of the diagnostic circuit unit and the output signal stored in the output data storage unit.