The invention relates to a microchip with a multiplicity of reconfigurable test structures, wherein the microchip has a test input (TDI) and a test output (TDO), wherein the multiplicity of test structures can be connected to the test input (TDI) and the test output (TDO), wherein one intermediate memory is provided for each of the multiplicity of test structures, wherein each of the multiplicity of test structures can be tested separately and concurrently with the aid of the respective intermediate memory and a corresponding individual control.

A method for testing storage protection hardware includes receiving by a non-trusted entity that is executing on a host server, a request to dispatch a secure entity. It is determined, by a secure interface control of the host server, whether the host server is in an auxiliary-secure (AS) debug mode for testing an AS entity. Based on determining that the host server is in the AS debug mode, a secure guest entity state is loaded from a state descriptor for the secure entity into an AS entity state in hardware to test, upon dispatch of the secure entity, accesses to pages in a memory that are registered as secure and as belonging to the AS entity.

A method for processing events logged as abnormal in a computer log includes collecting logs as to abnormal events of an electronic device, comparing such log with log data on a cloud server, determining whether the log data matches events logged as abnormal, and obtains log data if such log data matches information as to logged events identified as abnormal. The disclosure also provides an electronic device and a cloud server applying the method.

Provided are a device for providing a response operation corresponding to a device usage inquiry and a method of controlling the device. The method of controlling a device for providing a response operation corresponding to a device usage inquiry may include: receiving a user input corresponding to the device usage inquiry; classifying the device usage inquiry by analyzing the received user input corresponding to the device usage inquiry; extracting operation scenario information corresponding to a result of the classifying the device usage inquiry; and executing preset response operations of the device based on the operation scenario information, wherein the classifying includes classifying the device usage inquiry by inputting the user input of the device usage inquiry to a learning model that is a pre-generated.

A system for capturing a trace of an NVME hard disc can include a BMC, a BIOS, a protocol analysis instrument, and a fixture plate comprising a processor and a dial switch. The BIOS is configured to acquire register error information of the PCIe link when an error occurs to a PCIe link where the NVME hard disc is located, and send the register error information to the BMC, and the BMC is configured to send the received information to the fixture plate, and the fixture plate is configured to trigger the protocol analysis instrument to capture a PCIe trace of the NVME hard disc when a current error type corresponding to the dial switch is consistent with the error type of the register error information parsed by a processor of the fixture plate.

A tester including an interface configured to interface with an electronic device and a logic circuit. The logic circuit includes a pattern generator and at least one finite-state machine and is configured to sequentially acquire read data from the electronic device at sequential testing points of a testing range for evaluating an operating parameter of the electronic device or the tester until a set of consecutive passing points having a first passing point and a last passing point is identified, in response to identifying the first passing point, write data within the logic circuit of the tester identifying the first passing point, in response to identifying the second passing point, write data within the logic circuit of the tester identifying the second passing point, and output only data identifying the first passing point and data identifying the last passing point to a software application.

The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

Embodiments of information handling systems (IHSs) and methods are provided herein to automatically detect failure(s) on one or more power rails provided on a system motherboard of an IHS. One embodiment of such a method may include determining if a power rail test should be performed each time an information handling system (IHS) is powered on or rebooted. If a power rail test is performed, the method may perform a current measurement for each of the power rails separately to obtain actual current values for each power rail, compare the actual current values obtained for each power rail to expected current values stored for each power rail, and detect a failure on at least one of the power rails if the actual current value obtained for the at least one power rail differs from the expected current value stored for the at least one power rail by more than a predetermined percentage or amount.

Embodiments of this application disclose a fault detection method, and relate to the field of computer technologies. The method according to embodiments of this application includes: obtaining a scheduling table of a target task, where the scheduling table is used to indicate at least one test pattern, the at least one test pattern is used to detect a fault in a target logic circuit, and the target logic circuit is a logic circuit configured to execute the target task; and executing the at least one test pattern based on the scheduling table, to detect the fault in the target logic circuit. By determining the scheduling table of the target task, the test pattern included in the scheduling table is executed, so that execution of all test patterns in a software test library can be avoided. This reduces load of a processor, and effectively improves working efficiency of the processor.

A method of simulating device state changes in an integrated system includes receiving a transaction request from a client device, storing the transaction request as a first event in an event log, transmitting the transaction request to a terminal device, storing the transmission of the transaction request as a second event in the event log, receiving a device response from the terminal device, storing the device response as a third event in the event log, and when the integrated system is under test, a simulator replays the stored events in the integrated system under test.