A method of simulating device state changes in an integrated system includes receiving a transaction request from a client device, storing the transaction request as a first event in an event log, transmitting the transaction request to a terminal device, storing the transmission of the transaction request as a second event in the event log, receiving a device response from the terminal device, storing the device response as a third event in the event log, and when the integrated system is under test, a simulator replays the stored events in the integrated system under test.

The present disclosure provides a hard disk indicator circuit and a hard disk backplane. The hard disk indicator circuit includes an indicating unit, a control unit, a drive unit and a verification unit. The indicating unit indicates state of the hard disk. The control unit detects the state of the hard disk and outputting a control signal according to the state of the hard disk. The drive unit receives the control signal and lights the indicating unit according to the control signal. The verification unit obtains a level value of the indicating unit and determines whether the indicating unit is faulty according to the level value and the control signal. The present disclosure can quickly and accurately obtain the fault state of the hard disk indicator, save manpower and improve the fault detection efficiency.

This disclosure concerns a medical device designed for delivering a medical fluid or designed for controlling delivery of a medical fluid, and to a method of operating such a medical device. The medical device comprises a user interface associated with an electronic circuit connected to a first port and to a second port of a controller. The electronic circuit enables the controller to detect actuation of the user interface. The controller is configured to execute the following sequence of steps: first step: configure the first port as an output port and to apply a first signal to the first port; second step: to acquire a second signal from the second port; and third step: to determine on the basis of the second signal if a short circuit has occurred and to generate a short circuit alert signal if applicable.

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.

A tester including an interface configured to interface with an electronic device and a logic circuit. The logic circuit includes a pattern generator and at least one finite-state machine and is configured to sequentially acquire read data from the electronic device at sequential testing points of a testing range for evaluating an operating parameter of the electronic device or the tester until a set of consecutive passing points having a first passing point and a last passing point is identified, in response to identifying the first passing point, write data within the logic circuit of the tester identifying the first passing point, in response to identifying the last passing point, write data within the logic circuit of the tester identifying the last passing point, and output only data identifying the first passing point and data identifying the last passing point to a software application.

A method of simulating device state changes in an integrated system includes receiving a transaction request from a client device, storing the transaction request as a first event in an event log, transmitting the transaction request to a terminal device, storing the transmission of the transaction request as a second event in the event log, receiving a device response from the terminal device, storing the device response as a third event in the event log, and when the integrated system is under test, a simulator replays the stored events in the integrated system under test.

A system for capturing a trace of an NVME hard disc can include a BMC, a BIOS, a protocol analysis instrument, and a fixture plate comprising a processor and a dial switch. The BIOS is configured to acquire register error information of the PCIe link when an error occurs to a PCIe link where the NVME hard disc is located, and send the register error information to the BMC, and the BMC is configured to send the received information to the fixture plate, and the fixture plate is configured to trigger the protocol analysis instrument to capture a PCIe trace of the NVME hard disc when a current error type corresponding to the dial switch is consistent with the error type of the register error information parsed by a processor of the fixture plate.

A method of simulating device state changes in an integrated system includes receiving a transaction request from a client device, storing the transaction request as a first event in an event log, transmitting the transaction request to a terminal device, storing the transmission of the transaction request as a second event in the event log, receiving a device response from the terminal device, storing the device response as a third event in the event log, and when the integrated system is under test, a simulator replays the stored events in the integrated system under test.

Negative path testing in a bootloader environment can include backing up a global state of a component under test, injecting a fault to trigger an error in the component under test in a bootloader environment, executing error handling instructions until a checkpoint of the component under test in the bootloader environment is reached, restoring the global state to the component under test from the backup, and restarting the component under test.