Responsive to determining that a step in an interaction sequence has below a threshold similarity to any step in a set of log sequences, a first log entry is caused to be generated. The first log entry is emitted responsive to execution of the step in the interaction sequence by the software application. Responsive to determining that a starting key action lacks a corresponding ending key action, a second log entry is caused to be generated. The second log entry is emitted responsive to execution of code related to the corresponding ending key action by the software application. Responsive to determining, using a trained anomaly detection model, that a keyword related to an injected fault is not present in resulting fault log data, a third log entry is generated. The third log entry is emitted responsive to execution of code related to the keyword by the software application.

Several methods may be used to exploit the natural physical variations of sensors, to generate cryptographic physically unclonable functions (PUF) that may strengthen the cybersecurity of microelectronic systems. One method comprises extracting a stream of bits from the calibration table of each sensor to generate reference patterns, called PUF challenges, which can be stored in secure servers. The authentication of the sensor is positive when the data streams that are generated on demand, called PUF responses, match the challenges. To prevent a malicious party from generating responses, instructions may be added as part of the PUF challenges to define which parts of the calibration tables are to be used for response generation. Another method is based on differential sensors, one of them having the calibration module disconnected. The response to a physical or chemical signal of such a sensor may then be used to authenticate a specific pair of sensors.

An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.

A verification system of a basic input output system and a verification method thereof are provided. The verification system includes a server, a microcontroller, and a verification device. The server includes a platform controller hub and the basic input output system. The server outputs a log file of the basic input output system by a system management bus controller in the platform controller hub. The microcontroller is coupled to the server. The microcontroller receives the log file and converts the log file into a readable character. The verification device is coupled to the microcontroller. The verification device receives and displays the readable character.

Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Examples of electronic devices are described herein. In some examples, an electronic device may include a communication interface to receive information from a peripheral device. In some examples, the electronic device may include logic circuitry to determine a target latency tolerance reporting (LTR) value based on the information via a machine learning model.

There are disclosed various methods, apparatuses and computer program products for a testing apparatus. In accordance with an embodiment the testing apparatus comprises a frame; a gripping head for gripping a device to be tested; a first movement element for moving the gripping head with respect to the frame; a movement detector to detect at least one of a location and a position of the device; a touching element for touching the device; an imaging device for capturing images of the device; a display for generating visual information for capturing by the device; a set of sensors for examining operations of the device; a set of actuators for providing signals for reception by the device; and a set of plugs adapted to be inserted into a socket of the device.

Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.

Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.