Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.

A memory system includes a memory device including plural non-volatile memory blocks and a controller configured to determine whether a first memory block among the plural non-volatile memory blocks is re-usable after the first memory block is determined to be a bad block and copy second block information associated with a second memory block including a second program sequence number within a set range of a first program sequence number in the first memory block to first block information of the first memory block.

Techniques for automatically selecting device tests for testing devices configured for operation in wireless communication networks, based upon maintenance releases (MRs) received from original equipment manufacturers. When an MR with changes for a device is received, the MR may be analyzed in order to determine what the changes pertain to with respect to the device. The changes may be clustered with respect to requirements for the changes and a knowledge base may be consulted by a recommendation engine in order to determine candidate tests for testing the MR. The candidate tests may be based upon previous tests, failed tests and, relevant tests. Based at least in part on the identified previous tests, failed tests and relevant tests, one or more tests may be selected for testing devices with respect to the newly received MR.

The present disclosure provides a detection method and a detection device of a wafer testing machine, the detection method includes: storing an original test data tested by multiple wafer testing machines into a database; sifting out target test data from the original test data according to preset sifting conditions; performing statistics on the target test data sifted; and dividing the multiple wafer testing machines into comparison machines and machines to-be-detected; comparing whether there is significant difference between a target test data of each of the machine to-be-detected and a target test data of the comparison machine, in a corresponding test item within a first predetermined number of days; and performing statistics on number of days when each of the machines to-be-detected has significant difference; marking each of the machines to-be-detected, according to a statistical number of days when each machine to-be-detected has a significant difference.

Examples described herein provide a method for testing a memory associated with a processing system of an aircraft. The method includes performing, during operation of the processing system, an operational built-in test on the memory. The method further includes, responsive to detecting an error in the memory during the operational built-in test, performing a focused memory test at a location in the memory of the error. The method further includes, responsive the error being confirmed by the focused memory test, causing the processing system to be taken offline.

A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

Examples for servicing a computing device by a servicing agent are described. In an example, the servicing agent receives a first set of information which includes device information corresponding to the computing device. Further, the servicing agent receives a second set of information during a second session, wherein the second set of information is received through a user input and is indicative of a state of the computing device. The servicing agent further processes the first set of information and the second set of information to determine a diagnostic test. The servicing agent causes to execute the diagnostic test on the computing device.

Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.

A data processing apparatus is provided that includes storage circuitry that stores a plurality of future time series forecasters of an aspect of a system and, for each of the future time series forecasters, a representation of a confidence interval associated with that future time series forecaster. Unknown-unknown detection circuitry determines whether a new measurement falls outside confidence intervals generated from the representation of the confidence interval associated with each future time series forecaster of the aspect of the system, and in response to the new measurement falling outside the confidence intervals, labels the new measurement as an unknown-unknown.