Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.

A USB integrated circuit (IC), a testing platform and an operating method for USB integrated circuit are provided. The USB integrated circuit includes a USB port physical layer (PHY) circuit, a first lane adapter, a second lane adapter, a routing circuit, and a USB transport layer circuit. The USB PHY circuit is configured to transmit a differential signal between the USB integrated circuit and an outside device. When the USB integrated circuit operates in a testing mode, the routing circuit electrically connects the first lane adapter to the USB PHY circuit. When the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second lane adapter to the USB PHY circuit. The USB transport layer circuit is coupled to the first lane adapter and the second lane adapter.

A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.

This application provides a testing method and a testing device to determine a problem source of a server failure. When a server experiences a failure, one or more than one Electro Magnetic Susceptibility (EMS) tests are performed and the time domain waveforms during an EMS test are compared to determine whether the server failure is related to EMS interference.

An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

A baseboard management controller (BMC) may be configured to enable a communication interface from the BMC to a host processor on a host computing device and provide input to the host processor via the communication interface. The input causes at least one diagnostic operation to be performed on the host computing device. The BMC may collect host information in response to the diagnostic operation(s) being performed. The BMC may report the host information to another entity and/or store the host information in persistent memory within the BMC. In some embodiments, the input may be provided to the host processor in response to receiving a signal from a fabric controller. In some embodiments, the input may be provided to the host processor in response to detecting an anomaly associated with the host computing device. The BMC may take at least one action to mitigate the anomaly.

The present disclosure discloses an automated integrated test system and method thereof. A virtual mobile device is generated by a host at the test end at an initial time, which executes a preset script file to call the basic functions and the control functions after detecting the abnormal signals of production equipments, so as to simulate the processing flow of abnormal signals and to remotely adjust the equipment parameters. Then, a log file is generated according to the execution result of the script file, and the corresponding report files are generated according to different time ranges in the log file for transmission or display, so as to achieve the technical effect of improving the convenience of system testing in the complex environment.

A system for equivalence class analysis-based automated requirements-based test case generation includes a control processor, a data store containing textual design requirements, a textual converter unit structured to convert the textual design requirements to a machine-readable version of design requirements, a requirement partition unit configured to partition the machine-readable design requirements into one or more sets of related design requirements, an equivalence class partition unit configured to process the machine-readable design requirements and input/output variables into a set of equivalence classes, an equivalence class analyzer unit structured to analyze the set of equivalence classes to generate equivalence class tests and identify uncovered input space, and a boundary class analyzer unit structured to identify boundaries of the equivalence classes and generate boundary value tests and robustness tests. A method for equivalence class analysis-based automated requirements-based test case generation implementable on the system, and a non-transitory computer readable medium are also disclosed.

Provided are a computer program product, system, and method for using system errors and manufacturer defects in system components causing the system errors to determine a quality assessment value for the components. A system error message indicates at least one at least one system error resulting from an operation of at least one component deployed in the system. A manufacturing defect for the at least one component whose operation results in the at least one system error is determined from information from a manufacturer of the component. A quality assessment value is determined from the system error and manufacturing defect, for each of the at least one component for which there is a manufacturing defect. A message is transmitted to an administrator of the system indicating a negative assessment of the component in response to a comparison of the quality assessment value and a threshold value indicate a negative assessment.

A method and system for providing a self-test configuration in a device is disclosed. The method and system comprise providing a self-test mechanism in a kernel space of a memory and enabling a hook in a user space of the memory, wherein the hook is in communication with the self-test mechanism. The method and system also include running the self-test driver and utilizing the results.