G06F11/2289

CLOUD SIMULATION AND VALIDATION SYSTEM
20200349041 · 2020-11-05 ·

Cloud simulation or validation system allows for the simulation of a future node that may be deployed on a piece of hardware. The system may attempt to simulate the operating system for node-A on top of the hardware for node-A, including basic network connectivity. When a host is booted up with the simulated configuration, validation scripts may be run to verify that the site is correctly prepped for cloud deployment. With its pre-staged RAM-based OS temporarily loaded into the host's RAM memory, any set of OS-based scripts, tools or binaries, may be executed for simulation and validation based upon the intended role of the host onto which the cloud simulation or validation system configuration is loaded.

Failover method, apparatus and system

A failover method, apparatus and system to implement fast failover between a primary processor and a secondary processor, where the method includes receiving, by a first device, transaction content of a transaction and transaction status data of the transaction, the transaction status data being used to resume the transaction when the transaction is interrupted by a failure of a second device, and continuing to process, by the first device, the transaction according to the transaction content and the transaction status data when detecting that the second device fails.

Methods, apparatuses and systems for cloud-based disaster recovery test

A method, apparatus and system for providing a cloud-based disaster recovery test include receiving, at a cloud-based computing platform, a request for a disaster recovery test of at least a portion of a client's data network, in response to the received request, creating an isolated network in the cloud-based computing platform, cloning, in the isolated network, machines and configurations of the at least the portion of the client's data network to be included in the cloud-based disaster recovery test, reserving resources of the cloud-based computing platform based on the cloned machines and configurations of the at least the portion of the client's data network and an associated data handler to be deployed in the cloud-based disaster recovery test, and enabling the cloned machines for use by the client for performing the cloud-based disaster recovery test in the cloud-based computing platform.

METHOD AND APPARATUS FOR TUNING ADJUSTABLE PARAMETERS IN COMPUTING ENVIRONMENT
20200293835 · 2020-09-17 ·

Disclosed is a computer implemented method carried on an IT framework and a relative apparatus including: an orchestrator module; an optimizer module; a configurator module; a load generator module; and a telemetry module. The method includes: identifying tunable parameters representing a candidate configuration for the System Under Test (SUT), and applying the candidate configuration to the SUT using the configurator module; performance testing the SUT to determine a performance indicator; supplying performance metrics to the optimizer module's machine learning model to generate an optimized candidate configuration. The model provides as output, in correspondence of a candidate set of parameters, an expected value of the performance indicator and a prediction uncertainty thereof, used by the optimizer module to build an Acquisition Function used to derive a candidate configuration and by the load generator module to build the test workload. The test workload is computed through the machine learning model.

Memory device with internal measurement of functional parameters

A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.

VALIDATION OF CROSS LOGICAL GROUPS IN A NETWORK
20200186425 · 2020-06-11 ·

Disclosed are systems, methods, and computer-readable media for assuring tenant forwarding in a network environment. Network assurance can be determined in layer 1, layer 2 and layer 3 of the networked environment including, internal-internal (e.g., inter-fabric) forwarding and internal-external (e.g., outside the fabric) forwarding in the networked environment. The network assurance can be performed using logical configurations, software configurations and/or hardware configurations.

Bandwidth test in networking System-on-Chip verification

Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.

METHOD FOR DETECTING A DISRUPTION IN A VEHICLE'S COMMUNICATION SYSTEM BY CHECKING FOR ABNORMALITIES IN COMMUNICATION
20200162361 · 2020-05-21 ·

A system for detecting a disruption in a communication system of a vehicle. The system includes a vehicle bus and an electronic processor. The electronic processor is configured to receive a message, from a vehicle bus. The message has a format and a plurality of signals. The electronic processor is configured to detect anomalies in a bus identifier, the message format, a time the message is received, and a signal parameter of a signal of the plurality of signals. The electronic processor is also configured to generate an error if an anomaly is detected in the message format, an anomaly is detected in the time the message is received, or an anomaly is detected in the signal parameter of the signal of the plurality of signals.

Systems and methods to service an electronic device

The disclosed embodiments include systems and methods to service an electronic device. In one embodiment, the method includes receiving a request to service an electronic device communicatively connected to a test station. The method also includes obtaining a device model and an image group of the electronic device and determining criteria to service the electronic device in accordance with a desired setup, where each image group is associated with one or more different device models. The method further includes transmitting a request to service the electronic device to a management system having an image of applications compatible with the image group of the electronic device. The method further includes receiving at least one of a virtual hard drive storing a copy of the image of the applications and an indication of a location of the virtual hard drive. The method further includes executing the applications to service the electronic device.

Latency test in networking system-on-chip verification

Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.