Memory device with internal measurement of functional parameters

Abstract

A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.

Claims

1. A memory device comprising a built-in-self test timing circuit configured to generate a numerical value indicative of a timing parameter within the memory device, the built-in-self test timing circuit comprising: a first selection circuit configured to select a start signal from a plurality of start signals, the start signal being indicative of a start of an execution of a first memory operation within the memory device; a second selection circuit configured to select a stop signal from a plurality of stop signals, the stop signal being indicative of an end of the execution of the first memory operation within the memory device; a third selection circuit configured to select a synchronization signal from a plurality of synchronization signals, the synchronization signal being indicative of a frequency of operation of a processing circuit configured to execute the first memory operation; and a controllable logic circuit configured to receive the start signal, the stop signal, and the synchronization signal, the controllable logic circuit being further configured to determine a time elapsed between a reception of the start signal and a reception of the stop signal when the controllable logic circuit is in a first mode, the controllable logic circuit being further configured to determine a period of the synchronization signal when the controllable logic circuit is in a second mode.

2. The memory device of claim 1, wherein the controllable logic circuit comprises: logic circuitry configured to receive the start signal, the stop signal, and the synchronization signal, the logic circuitry being further configured to output a first counting signal between the reception of the start signal and the reception of the stop signal when the controllable logic circuit is in the first mode, the logic circuitry being further configured to output a second counting signal between consecutive falling edges or consecutive rising edges of the synchronization signal when the controllable logic circuit is in the second mode; and a control circuit configured to place the logic circuitry in the first mode or the second mode based on an instruction received by the memory device.

3. The memory device of claim 2, wherein the controllable logic circuit further comprises: counting circuitry configured to receive a reference periodic signal, the counting circuitry being further configured to receive the first counting signal when the logic circuitry is in the first mode and to determine a number of cycles of the reference periodic signal present during a time the first counting signal is received by the counting circuitry.

4. The memory device of claim 3, wherein the time between the reception of the start signal and the reception of the stop signal by the logic circuitry is configured to be greater than a period of the reference periodic signal.

5. The memory device of claim 3, wherein the counting circuitry is further configured to receive the second counting signal when the logic circuitry is in the second mode and to determine a number of cycles of the reference periodic signal present during a time the second counting signal is received by the counting circuitry.

6. The memory device of claim 5, wherein a frequency of the reference periodic signal is configured to be greater than a frequency of the synchronization signal.

7. The memory device of claim 2, wherein the control circuit is further configured to generate a first selection signal and a second selection signal based on the instruction received by the memory device, the control circuit being further configured to provide the first selection signal and the second selection signal to the first selection circuit and the second selection circuit, respectively, the first selection signal and the second selection signal being configured to control a selection of the start signal and the stop signal by the first selection circuit and the second selection circuit, respectively.

8. The memory device of claim 1, further comprising: processing circuitry configured to enable execution of the first memory operation; and a non-volatile memory communicatively coupled with the processing circuitry.

9. A memory device comprising a built-in-self test timing circuit configured to generate a numerical value indicative of a timing parameter within the memory device, the built-in-self test timing circuit comprising: a first selection circuit configured to select a first start signal from a plurality of start signals based on a first selection signal, the first start signal being indicative of a start of an execution of a first memory operation within the memory device; a second selection circuit configured to select a first stop signal from a plurality of stop signals based on a second selection signal, the first stop signal being indicative of an end of the execution of the first memory operation within the memory device; a third selection circuit configured to select a first synchronization signal from a plurality of synchronization signals based on a third selection signal, the first synchronization signal being indicative of a frequency of operation of a processing circuit configured to execute the first memory operation; and a parameter measurement circuit configured to operate in a first configuration and a second configuration different from the first configuration and to determine a period of a scaled version of the first synchronization signal when the parameter measurement circuit is operating in the second configuration, the parameter measurement circuit being configured to, when the parameter measurement circuit is operating in the first configuration, receive the first start signal and the first stop signal and determine a time elapsed between a reception of the first start signal and a reception of the first stop signal, and when the parameter measurement circuit is operating in the second configuration, receive the first synchronization signal and determine a period of the first synchronization signal.

10. The memory device of claim 9, wherein the built-in-self test timing circuit further comprises: a control circuit configured to place the parameter measurement circuit in the first configuration or the second configuration based on an instruction received by the memory device, the control circuit being further configured to generate the first selection signal and the second selection signal based on the instruction received by the memory device.

11. The memory device of claim 9, wherein the parameter measurement circuit comprises: a first logic circuit configured to receive the first start signal and the first stop signal, the first logic circuit being further configured, when the parameter measurement circuit is operating in the first configuration, to start an output of a first counting signal in response to receiving the first start signal and to stop the output of the first counting signal in response to receiving the first stop signal; a second logic circuit configured to receive the first counting signal and to output a reference periodic signal in response to receiving the first counting signal; and a counter configured to determine a number of cycles of the reference periodic signal present during a time the first counting signal is received by the second logic circuit.

12. The memory device of claim 11, wherein a time between the reception of the first start signal and the reception of the first stop signal by the first logic circuit is configured to be greater than a period of the reference periodic signal.

13. The memory device of claim 9, wherein the built-in-self test timing circuit further comprises a frequency scaling circuit configured to scale a frequency of the first synchronization signal to produce the scaled version of the first synchronization signal.

14. The memory device of claim 9, wherein a frequency of the scaled version of the first synchronization signal is configured to be less than a frequency of a reference periodic signal.

15. The memory device of claim 9, further comprising: processing circuitry configured to enable execution of the first memory operation; and a memory communicatively coupled with the processing circuitry.

16. The memory device of claim 15, wherein the memory comprises a non-volatile memory.

17. A method, comprising: receiving an instruction for execution of a first memory operation within a memory device; generating a first selection signal and a second selection signal based on the instruction; placing a parameter measurement circuit in a first mode or a second mode based on the instruction, the parameter measurement circuit being configured to determine a timing parameter; selecting a first start signal from a plurality of start signals based on the first selection signal, the first start signal being indicative of a start of an execution of the first memory operation; selecting a first stop signal from a plurality of stop signals based on the second selection signal, the first stop signal being indicative of an end of the execution of the first memory operation; providing the first start signal and the first stop signal to the parameter measurement circuit; determining, by the parameter measurement circuit, a time elapsed between a reception of the first start signal and a reception of the first stop signal based on a reference periodic signal, when the parameter measurement circuit is in the first mode; determining, by the parameter measurement circuit, a period of a synchronization signal based on the reference periodic signal, when the parameter measurement circuit is in the second mode; generating a third selection signal based on the instruction; selecting the synchronization signal from a plurality of synchronization signals based on the third selection signal, the synchronization signal being indicative of a frequency of operation of a processing circuit configured to execute the first memory operation; and providing the synchronization signal to the parameter measurement circuit.

18. The method of claim 17, wherein a frequency of the synchronization signal is configured to be less than a frequency of the reference periodic signal.

19. The method of claim 17, wherein a time between the reception of the first start signal and the reception of the first stop signal by the parameter measurement circuit is configured to be greater than a period of the reference periodic signal.

20. The method of claim 17, further comprising: outputting a counting signal between the reception of the first start signal and the reception of the first stop signal based on the instruction for execution of the first memory operation within the memory device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of a test apparatus wherein an embodiment of the present invention may be applied.

(2) FIG. 2 is a schematic diagram of a non-volatile memory device according to an embodiment of the present invention.

(3) FIG. 3 is a schematic diagram of a circuit of a measure block of a memory device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(4) The approach according to one or more embodiments, as well as further features and the advantages thereof, will be best understood with reference to the following detailed description, given purely by way of a non-restrictive indication, to be read in conjunction with the accompanying drawings, wherein corresponding elements are denoted with equal or similar references, and their explanation is not repeated for the sake of exposition brevity.

(5) With particular reference to FIG. 1, a test apparatus 100 is schematically illustrated wherein an embodiment may be applied. The test apparatus 100 may perform a parametric test on a plurality of non-volatile memory devices 105 (or simply memory devices, only one shown in the figure), to obtain a characterization thereof, i.e. to determine a measure value (or measure) of specific functional parameters. More particularly, the parametric test may be used for measuring a plurality of time functional parameters (e.g., band-gap time, reading access time, and clock frequency of charge pumps), each one associated (or associatable) with a corresponding predefined memory operation of the memory device 105 (e.g., generation of a band-gap voltage, reading of a memory address, and charge pumps activation, respectively).

(6) The test apparatus 100 includes a test driver circuit (test driver) 110 for providing and receiving information in the form of electrical signals. In particular, the test apparatus 100 provides a measure instruction for obtaining a measure value of a corresponding memory operation within the memory device 105. To this end, the test driver no is coupled with input terminals T.sub.IN, only one shown for simplicity, and output terminals T.sub.OUT, only one shown for simplicity, of each memory device 105 through a coupling block 115 (e.g., a probe card, not shown in the figure, including a printed circuit board and a plurality of electrically conductive probes, such as for the EWS testing).

(7) The measure instruction is typically encoded by a string of binary digits (or bits) according to a known communication protocol. The corresponding result is represented by a numeric value encoded by another string of bits.

(8) Turning now to FIG. 2, a memory device 205 (e.g., a non-volatile memory device, such as a flash memory device) according to an embodiment is schematically illustrated. In the following, for the sake of exposition, brevity, and clarity, only functional blocks (relevant to the embodiment) directly or indirectly involved in the measure of significant functional parameters of the memory device 205 are introduced and described.

(9) The memory device 205 includes, in addition to the terminal T.sub.IN for receiving the measure instruction and to the terminal T.sub.OUT for providing the measure value, a memory matrix 210 for storage purposes, and a plurality of peripheral circuits (not shown) for management and access thereto. The memory device 205 also includes a control block 215, which, by interfacing with the memory matrix 210 (connection not shown) and the peripheral circuits, generally controls functions of the memory device 205. For example, the control block 215 is able, in a known manner, to provide a plurality of time signals. The time signals may be logically divided into groups (of one or more time signals), each one of which is indicative of the execution of a corresponding selected memory operation (i.e., performed by the memory device 205 according to the measure instruction received at the terminal T.sub.IN). Such time signals may include both status signals relating to a status of the execution of the selected memory operation, and synchronization signals (or clock signals) S.sub.CLOCKi (with i=1, 2 . . . n).

(10) More particularly, the status signals may include a set of start signals S.sub.STARTi (with i=1, 2 . . . n), each one indicative of a start of the execution of a corresponding selected memory operation, and a plurality of stop signals S.sub.STOPi (with i=1, 2 . . . n), each one indicative of a stop of the execution of a corresponding selected memory operation. Therefore, for each selected memory operation, the control block 215 may provide a pair of signals S.sub.STARTi, S.sub.STOPi relating to the status of the execution of the selected memory operation and/or the signal S.sub.CLOCKi relating to the synchronization of one or more of the peripheral circuits involved therein.

(11) The memory device 205 may further include a measure block 220 for receiving the signals S.sub.STARTi, S.sub.STOPi, S.sub.CLOCKi and determining the measure of the time parameter according to one or more of such signals S.sub.STARTi, S.sub.STOPi, S.sub.CLOCKi. Therefore, advantageously, the memory device 205 may provide the terminal T.sub.OUT (and thus directly the test apparatus) with a numerical measure value of the functional parameter, and not the result of the corresponding selected memory operation (that would involve additional processing for obtaining the measure value from it).

(12) Referring now to FIG. 3, a circuit implementation of the measure block 220 according to an embodiment is illustrated. The measure block 220 includes three multiplexers 225a, 225b and 225c, each one having n input terminals, an output terminal, and a selection terminal. In particular, the multiplexer 225a, 225b, 225c receives the signals S.sub.STARTi, S.sub.STOPi, S.sub.CLOCKi, respectively, at its input terminals and provides a selected one of such signals to its output terminal according to a corresponding selection signal S.sub.SELa, S.sub.SELb, S.sub.SELc received at the selection terminal.

(13) The measure block 220 further includes a logic inverter 230a (for example, in CMOS logic) and another logic inverter 230b similar to the logic inverter 230a. The logic inverter 230a, 230b is connected to the output terminal of the multiplexer 225a,225b for receiving the selected signal S.sub.STARTi, S.sub.STOPi and providing a corresponding signal S.sub.STARTi, S.sub.STOPi negated with respect to the selected signal S.sub.STARTi, S.sub.STOPi.

(14) The measure block 220 includes two further multiplexers 235a and 235b each one having two input terminals, an output terminal, and a selection terminal. In particular, an input terminal of the multiplexer 235a, 235b is connected to the output terminal of the multiplexer 225a, 225b, whereas the other input terminal of the multiplexer 235a, 235b is connected to the output terminal of the logic inverter 230a, 230b. In this way, the multiplexers 235a and 235b receive the signals S.sub.STARTi, S.sub.STARTi, and the signals S.sub.STOPi, S.sub.STOPi at the respective input terminals, and provide a selected one of such signals (which hereinafter will be referred to as a functional start signal denoted by the reference S.sub.STARTi/S.sub.STARTi, and a functional stop signal denoted by the reference S.sub.STOPi/S.sub.STOPi, respectively) to the respective output terminal according to a selection signal S.sub.SELap, S.sub.SELbp received at the corresponding selection terminal. As will be explained more in detail in the following, the signal S.sub.SELap, S.sub.SELbp depends on a polarity with which the selected signal S.sub.STARTi, S.sub.STOPi has been implemented within the memory device.

(15) The measure block 220 further includes a scaling block 240 having an input terminal for receiving the selected signal S.sub.CLOCKi, at a corresponding frequency (representing the functional parameter to be measured), and an output terminal for providing a functional synchronization signal S.sub.CLOCKi,u at another frequency scaled with respect to the frequency of the selected signal S.sub.CLOCKi by a suitable scaling factor. As will be explained in the following, the scaling factor is such that the frequency of the signal S.sub.CLOCKi,u is compatible with a following counting operation. More specifically, such scaling factor depends on a ratio between a reference frequency of a reference synchronization signal S.sub.CLOCK,REF (for example, a periodic signal generated outside the memory device) and an assumed value of the frequency of the selected signal S.sub.CLOCKi (being known, since it may be theoretically close to the design value), which is adjustable within the scaling block 240 according to an appropriate regulation signal S.sub.REG.

(16) The measure block 220 further includes a logic block 245 including three input terminals connected to the output terminal of the multiplexer 235a, the output terminal of the multiplexer 235b and the output terminal of the scaling block 240, respectively. The logic block 245 also includes a configuration terminal for receiving a configuration signal S.sub.CONFIG, and an output terminal for providing a counting signal S.sub.CON according to the signals S.sub.STARTi/S.sub.STARTi, S.sub.STOPi/S.sub.STOPi, S.sub.CLOCKi,u and S.sub.CONFIG.

(17) The measure block 220 also includes an AND logic gate 250 (for example, in CMOS logic as well) having two input terminals and an output terminal, and a counter 255 of a known type connected to the output terminal of the AND logic gate 250 and coupled with the output terminal of the memory device (not shown) for providing the latter with the measure value of the time parameter. In particular, the AND logic gate 250 receives the signal S.sub.CON at an input terminal thereof and the signal S.sub.CLOCK,REF (used by the counter for counting) at the other input terminal. Finally, the measure block 220 includes a register block 260 for providing the signals S.sub.SEL, S.sub.SELb, S.sub.SELc, S.sub.SELap, S.sub.SELbp, S.sub.REG, S.sub.CONFIG (electrical connections are not shown for the sake of simplicity) according to the selected memory operation.

(18) The operating principle of the measure block 220 may be summarized as follows. As the memory device receives the measure instruction, the block 220 determines one between two possible configurations of the logic block 245 (according to the selected memory operation and according to a corresponding type of time functional parameter to be measured), i.e., a first configuration wherein the logic block 245 allows determining a duration of the selected memory operation, and a second configuration wherein the logic block 245 allows determining the clock frequency of one of the peripheral circuits of the memory device involved in the selected memory operation. This is performed by the register block 260, which, in response to the selected memory operation, asserts or de-asserts the signal S.sub.CONFIG for setting the (common) logic block 245 in the first configuration or in the second configuration, respectively, (or vice-versa without that, this, as will be understood, may alter the operating principle). In case the signal S.sub.CONFIG is asserted (first configuration), the register block 260 provides the signals S.sub.SELa, S.sub.SELb to the multiplexers 225a, 225b for selecting the signals S.sub.STARTi, S.sub.STOPi according to the memory operation defined within the measure instruction (e.g., band-gap voltage generation, reading of a predefined memory address, or the like).

(19) Before the start of the execution of the selected operation, such signals S.sub.STARTi, S.sub.STOPi are both de-asserted, but with a polarity that depends on how they have been implemented within the memory device (with the polarity information that is included within the register block 260). In general, the signals S.sub.STARTi may be asserted, all or in part, at the high or low logic level, as well as the signals S.sub.STOPi (with the signals S.sub.STOPi that may also have not the same polarity as the corresponding signals S.sub.STARTi). For this reason, according to the selected memory operation, the register block 260 provides the signals S.sub.SELap, S.sub.SELbp at the appropriate value to allow the multiplexers 235a and 235b to select the signal S.sub.STARTi or the signal S.sub.STARTi and the signal S.sub.STOPi or the signal S.sub.STOPi, respectively, according to a polarity of the logic block 245. For example, since the latter may be implemented according to any combinatorial and/or sequential logic circuit without the principles of the present embodiments becoming limited, where the logic block 245 is implemented by using active high latches (not shown), the signals S.sub.SELap, S.sub.SELbp may be such as to select one between the signal S.sub.STARTi and the signal S.sub.STARTi, and one between the signal S.sub.STOPi and the signal S.sub.STOPi that, at the start and stop of the selected memory operation, respectively, is asserted at the high logic level (and vice-versa in case of, for example, active low latches).

(20) At this point, at the assertion of the signal S.sub.STARTi/S.sub.STARTi, the logic block 245 asserts the counting signal (for example, to the high logic level), so that the signal S.sub.CLOCK,REF is received by the counter 255. The latter, in a known manner, performs a counting of the number of cycles of the signal S.sub.CLOCK,REF within a counting interval. Such counting interval may be defined as the time interval between the assertion of the signal S.sub.STARTi/S.sub.STARTi and the assertion of the signal S.sub.STOPi/S.sub.STOPi (in other words, the logic block 245 latches the asserted signal S.sub.CON until the end of the selected memory operation). In fact, when the signal S.sub.STOPi/S.sub.STOPi has been asserted, thereby indicating that the selected memory operation has ended, the logic block 245 de-asserts the signal S.sub.CON (for example, to the low logic level). This also may force the output of the AND logic gate 250 down to the low logic level, thus causing the interruption of the counting by the counter 255.

(21) At this point, the counter 255, whose counting is the measure value of the functional parameter, may send such measure value to the output terminal of the memory device, or process and/or store it for providing it later (e.g., at the end of the parametric test, possibly together with other measure values of the same or other memory operations).

(22) When the signal S.sub.CONFIG is de-asserted (second configuration), the register block 260 provides the signal S.sub.SELc to the multiplexer 225c for selecting the signal S.sub.CLOCKi according to the selected memory operation (for example, activation of the charge pumps), and the signal S.sub.REG to the multiplexer 235a for providing the signal S.sub.CLOCKi,u to the logic block 245 according to the scaling factor. In such second configuration, the logic block 245 may be sensitive to an edge of the received signal rather than a level thereof (such as in the first configuration). In particular, the logic block 245 asserts the signal S.sub.CON in response to a switching (for example, a rise edge) of the signal S.sub.CLOCKi,u (with such switching that, unless a possible phase shift introduced by the scaling block 240, corresponds to the switching of the selected signal S.sub.CLOCKi). This involves the start of the counting (by the counter 255) of the number of cycles of the signal S.sub.CLOCK,REF in a counting interval defined by a period of the signal S.sub.CLOCKi,u (time distance between two identical successive switchings, i.e. two rising edges in the example at issue). In this case, the counting provides the value of the period of the signal S.sub.CLOCKi,u, from which it may be possible to obtain the frequency thereof and hence the frequency of the signal S.sub.CLOCKi (e.g., by a suitable algebraic block, not shown, that computes the inverse of the period of the signal S.sub.CLOCKi,u, and performs an operation opposite to that of the scaling block 240).

(23) It should be noted that the scaling factor may be such that the frequency of the signal S.sub.CLOCK,REF is sufficiently greater than the frequency of the signal S.sub.CLOCKi,u to ensure that the period of the signal S.sub.CLOCKi,u includes a relatively high number (e.g., preferably from 10 to 100, still more preferably from 40 to 70, such as 55) of periods of the signal S.sub.CLOCK,REF (and to allow a more accurate counting of the period of the signal S.sub.CLOCKi,u and hence of the frequency thereof).

(24) The described approach is particularly advantageous as it calculates the measured value of a plurality of functional parameters by using a single measure block within the memory device. This allows that, during the parametric test, the apparatus may not need either complex test instructions (as the measured numeric value, being able to be provided directly to the test apparatus from the memory device, needs no further processing) or dedicated routines for each measure parameter. Therefore, the described memory device allows performing parametric tests that, as not providing for continuous interactions with the test apparatus, have shorter durations and are more efficient, with advantages in both economic and practical terms.

(25) Naturally, to satisfy local and specific requirements, a person skilled in the art may apply to the approach described above many logical and/or physical modifications and alterations. More specifically, although the present embodiments have been described with a certain degree of particularity, it should be understood that various omissions, substitutions and changes in the form and details as well as other embodiments are possible. In particular, different embodiments may even be practiced without the specific details (such as the numeric examples) set forth in the preceding description for providing a more thorough understanding thereof. On the contrary, well known features may have been omitted or simplified to not obscure the description with unnecessary particulars. Moreover, specific elements and/or method steps described in connection with any disclosed embodiment of the invention may be incorporated in any other embodiment as a matter of general design choice.

(26) For example, analogous considerations may apply if the memory device has a different structure or includes equivalent components. In any case, any component thereof may be separated into several elements, or two or more components may be combined into a single element. Moreover, each component may be replicated for supporting the execution of the corresponding operations in parallel. It should also be noted that any interaction between different components generally does not need to be continuous (unless otherwise indicated), and it may be both direct and indirect through one or more intermediaries. For example, the memory device may be provided with more than one control block. Each peripheral circuit of the memory device may be provided with its own control block for monitoring the status during the execution of the selected memory operation and providing the corresponding start, stop and synchronization signals.

(27) Moreover, although in the present description only two conductive terminals for exchanging electrical signals during the execution of the parametric test have been described and shown, the memory device may include several conductive terminals suitable for the purpose. For example, it may be possible to provide the use of an output terminal for providing the result of the operation, and further output terminals for providing the measure value and/or the start, stop and synchronization signals (for example, for using such signals in appropriate control algorithms for obtaining more precise measure values of the functional parameters). In addition, the memory device may store, in appropriate locations of the memory matrix or in properly configured registers, the measure values of a predefined number of functional parameters, and provide them (for example, serially through the output terminal) at the end (or at any phase) of the parametric test.

(28) The memory device may be of the FLASH, EPROM, or E.sup.2PROM type. The multiplexers may be implemented according to any technology deemed appropriate and/or by using conceptually equivalent techniques (or they may also be omitted in the case of individual time signals).

(29) The counter may be implemented in any useful manner, such as by flip-flops, and provide counting in binary, decimal, hexadecimal code, at 4 bits or 8 bits. The counter may also be provided with pins (for example, for zeroing it or selecting the type of code for the counting), accessible from outside of the memory device, or through the measure instruction.

(30) In addition, the logic inverters may not be present, for example, where the control block of the memory device already provides the negated start signal and the negated stop signal, or be present in greater numbers. In the latter case, one or more inverter chains may be provided for reconstructing edges and levels of the start signals and of the stop signals, to avoid degradation thereof. The logic block may be made in combinatory or sequential logic, or a combination thereof.

(31) The reference synchronization signal is not limiting for the present embodiments, and it may be any periodic signal (e.g., sine or square wave). Analogously, even the clock signals whose frequency it may be desirable to calculate (functional parameter) may be of a different type, or have reciprocally different swings. In the latter case, it may be possible to provide the use of circuits for making the swing of each synchronization signal uniform to the swing of the logic circuits (such as, for example, the one of the AND logic gate).

(32) The measure block may also include a control element that allows updating, after the measure of each clock frequency, the values with respect to the assumed values (i.e., the design values) within the register block. In any case, the band-gap time, the reading access time, and the clock frequency represent respective merely illustrative measure types, and therefore they should not be constructed in a limiting way. In this respect, the described approach may also be applied to other similar measures (e.g., programming time, erasing time, rise and/or falling time of input signals, time of data transfer to registers from the memory matrix, and the like), or for further measure types. In the latter case, it should be noted that the logic block may be implemented to provide additional configurations for allowing such further measure types (with the configuration signal that may be a binary code with an appropriate number of bits).

(33) Moreover, separate logical blocks may be provided for the different measure types (instead of a common one configurable in different way). Similar considerations apply if the test apparatus has a different structure or includes equivalent components (both separated to each other and combined together, in whole or in part).

(34) It should be readily understood that the proposed structure may be part of the design of an integrated circuit. The design may also be created in a programming language. Moreover, if the designer does not manufacture the electronic devices or the masks, the design may be transmitted by physical means to others. In any case, the resulting integrated circuit may be distributed by its manufacturer in raw wafer form, as a bare die, or in packages. Moreover, the proposed structure may be integrated with other circuits in the same chip, or it may be mounted in intermediate products (such as mother boards) and coupled with one or more other chips (such as a processor). In any case, the integrated circuit is suitable to be used in complex systems (such as automotive applications).

(35) Finally, the embodiments may be implemented through an equivalent method (by using similar steps, removing some steps being not essential, or adding further optional steps). Moreover, the steps may be performed in different order, concurrently or in an interleaved way (at least partly).