A processor-fault reproduction method includes: determining a heating time of a processor taken using a heating program which heats the processor to a fault occurrence temperature when a fault occurs from a current temperature based on first information regarding the current temperature of the processor, second information regarding a power consumption value and a temperature of the processor before the fault occurs and a refrigerant temperature of a cooling medium to cool the processor, third information regarding the fault occurrence temperature, and fourth information regarding a power consumption value of the processor during execution of the heating program; determining an execution time by adding a fault reproduction time taken by a fault reproducing program which reproduces a state of the processor when the fault occurs to the heating time; and reporting the execution time to a job scheduler with a request to execute the heating and fault reproducing programs.

In various examples, permanent faults in hardware component(s) and/or connections to the hardware component(s) of a computing platform may be predicted before they occur using in-system testing. As a result of this prediction, one or more remedial actions may be determined to enhance the safety of the computing platform (e.g., an autonomous vehicle). A degradation rate of a performance characteristic associated with the hardware component may be determined, detected, and/or computed by monitoring values of performance characteristics over time using fault testing.

A computer system includes a circuit board, one or more connectors/sockets and a first controller. The connectors/sockets are disposed on the circuit board. The first controller is configured to receive information corresponding to parameters of the circuit board and/or the connectors/sockets before booting up the computer system to run an operating system (OS).

A test circuit that includes a circuit to be calibrated, an error generation circuit, and a simplex circuit coupled to one another. The circuit to be calibrated is configured to implement a first plurality of trim codes as calibration parameters for a corresponding plurality of components of the circuit to be calibrated and generate a first actual output. The error generation circuit is configured to generate a first error signal based on a difference between the first actual output and an expected output of the circuit to be calibrated. The simplex circuit is configured to receive the first error signal from the error generation circuit, generate a second plurality of trim codes utilizing a simplex algorithm based on the first error signal, and transmit the second plurality of trim codes to the circuit to be calibrated.

A test circuit that includes a circuit to be calibrated, an error generation circuit, and a simplex circuit coupled to one another. The circuit to be calibrated is configured to implement a first plurality of trim codes as calibration parameters for a corresponding plurality of components of the circuit to be calibrated and generate a first actual output. The error generation circuit is configured to generate a first error signal based on a difference between the first actual output and an expected output of the circuit to be calibrated. The simplex circuit is configured to receive the first error signal from the error generation circuit, generate a second plurality of trim codes utilizing a simplex algorithm based on the first error signal, and transmit the second plurality of trim codes to the circuit to be calibrated.

An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.

An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.

A power supply diagnostic strategy for discrete power supply diagnostic states is independent of the underlying memory structure. The values used in the associated algorithm are selected to ensure that random linked failures will be detected. This applies to planar memory structures with 1, 2, 4, 6, 8, 12, and 16 common lattices, or physical memory structures with individual bit dispersed memories with 1, 2, 4, 6, 8, 12, and 16 consecutive bit splices. Further, the strategy provides that the various monitored voltage tables remains distinct even with compiler optimization activated.

A power supply diagnostic strategy for discrete power supply diagnostic states is independent of the underlying memory structure. The values used in the associated algorithm are selected to ensure that random linked failures will be detected. This applies to planar memory structures with 1, 2, 4, 6, 8, 12, and 16 common lattices, or physical memory structures with individual bit dispersed memories with 1, 2, 4, 6, 8, 12, and 16 consecutive bit splices. Further, the strategy provides that the various monitored voltage tables remains distinct even with compiler optimization activated.

It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency.