G06F11/25

SEMICONDUCTOR DEVICE
20170285106 · 2017-10-05 ·

A semiconductor device is provided with: a first circuit; a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit; a pattern-generator control circuit controlling each of the plurality of pattern generators; a pattern compressor compressing a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators; a pattern-compressor control circuit controlling the pattern compressor; and a self-diagnosis control circuit connected to the pattern-generator control circuit and the pattern-compressor control circuit, and controlling the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators.

SEMICONDUCTOR DEVICE
20170285106 · 2017-10-05 ·

A semiconductor device is provided with: a first circuit; a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit; a pattern-generator control circuit controlling each of the plurality of pattern generators; a pattern compressor compressing a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators; a pattern-compressor control circuit controlling the pattern compressor; and a self-diagnosis control circuit connected to the pattern-generator control circuit and the pattern-compressor control circuit, and controlling the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators.

CONDITION MONITORING DEVICE AND CONDITION MONITORING METHOD FOR EXTRACTED-GAS COMPRESSION SYSTEM, AND EXTRACTED-GAS COMPRESSION SYSTEM

A condition monitoring device for an extracted-gas compression system including a compressor which increases pressure of extracted gas includes: a sensor for detecting a state quantity of the extracted gas flowing into the compressor; an erosion progression level calculation unit for calculating an erosion progression level of the compressor on the basis of the state quantity of the extracted gas; and a service life evaluation unit for evaluating a service life of the compressor on the basis of the erosion progression level of the compressor.

CONDITION MONITORING DEVICE AND CONDITION MONITORING METHOD FOR EXTRACTED-GAS COMPRESSION SYSTEM, AND EXTRACTED-GAS COMPRESSION SYSTEM

A condition monitoring device for an extracted-gas compression system including a compressor which increases pressure of extracted gas includes: a sensor for detecting a state quantity of the extracted gas flowing into the compressor; an erosion progression level calculation unit for calculating an erosion progression level of the compressor on the basis of the state quantity of the extracted gas; and a service life evaluation unit for evaluating a service life of the compressor on the basis of the erosion progression level of the compressor.

Circuit for securing scan chain data
09746519 · 2017-08-29 · ·

Methods, devices and circuits are provided for protecting secure data from being read during a scan chain output. A plurality of scan flip-flops is coupled in a scan chain, and an input circuit is configured to shift input data to the scan flip-flops. A protection circuit is coupled to the scan flip-flops, and the protection circuit configured to detect scan-in of data from the input circuit to a designated one of the scan flip-flops. Scan-out of data from the designated scan flip-flop is enabled in response to detection of a scan-in of data from the input circuit to the designated scan flip-flop. Scan-out of data from the designated scan flip-flop is prevented in response to no detection of scan-in of data from the input circuit to the designated scan flip-flop.

Device And Method For Concurrently Analyzing A Plurality Of Telecommunications Signal Protocols
20170322858 · 2017-11-09 ·

An improved method for telecommunication analysis and monitoring employing a logic analyzer device. The logic analyzer device provides a plurality of concurrent graphic depictions of different electronic signals under differing electronic protocols for signal error determination on a communications channel. Error source determination is enabled through the provided concurrent depiction of digital and analog signal characteristics in the differing protocols, including digital data packets, signal voltages and timing. Through this concurrent depiction the user can visually discern potential causation for electronic communication errors caused by non-continuous signal anomalies affecting one or more of the protocols.

Device And Method For Concurrently Analyzing A Plurality Of Telecommunications Signal Protocols
20170322858 · 2017-11-09 ·

An improved method for telecommunication analysis and monitoring employing a logic analyzer device. The logic analyzer device provides a plurality of concurrent graphic depictions of different electronic signals under differing electronic protocols for signal error determination on a communications channel. Error source determination is enabled through the provided concurrent depiction of digital and analog signal characteristics in the differing protocols, including digital data packets, signal voltages and timing. Through this concurrent depiction the user can visually discern potential causation for electronic communication errors caused by non-continuous signal anomalies affecting one or more of the protocols.

Delayed authentication debug policy

A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

Delayed authentication debug policy

A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

Abnormality diagnosis system that reconfigures a diagnostic program based on an optimal diagnosis procedure found by comparing a plurality of diagnosis procedures
11397655 · 2022-07-26 · ·

The abnormality diagnosis system detects a failure sign of a device to be diagnosed. The abnormality diagnosis system includes: a diagnosis process search unit which searches for a suitable diagnosis processing procedure by comparing a plurality of diagnosis processing procedures, and outputs reconfiguration information corresponding to the suitable diagnosis processing procedure; and a diagnosis processing unit which has a reconfigurable processing unit and which uses the suitable diagnosis processing procedure found by the diagnosis process search unit to detect a failure sign of the device to be diagnosed by reconfiguring the processing unit on the basis of the reconfiguration information.