A testing device for real-time testing of at least a part of a virtual electronic control unit with an electronic control unit code is provided. The testing device has a computing unit of a first type, and a computing unit of a second type. The testing of a virtual electronic control unit with electronic control unit code, which is executable on the computing unit of the second type with a second instruction set, is made possible in that a computing unit of the first type executes an emulator for emulating the computing unit of the second type and the emulator executes the electronic control unit code. The emulator also has a simulation environment interface for exchanging data and/or events with the simulation environment.

A device verification system includes a device under test (DUT) including digital logic and a plurality of digital memories coupled to the digital logic; a plurality of hardware Verification Intellectual Property (VIP) modules coupled to the DUT to verify hardware of the DUT; and a plurality of software VIP modules coupled to the DUT to verify firmware of the DUT. A method for verifying the functionality of a device under test includes automatically developing code segments representing a series of firmware test patterns with a software Verification Intellectual Property (VIP) module; transferring code segments representing the series of firmware test patterns into a digital memory of a device under test (DUT) that includes digital logic; and monitoring the functional operation of the DUT as it uses the digital logic to execute the code segments representing the series of firmware test patterns stored in digital memory.

Aspects disclosed in the detailed description include a microprocessor fault detection and response system. The microprocessor fault detection and response system utilizes a hardware-based fault-attack aware microprocessor extension (FAME) and a software-based trap handler for detecting and responding to a fault injection on a microprocessor. Upon detecting the fault injection, the hardware FAME switches the microprocessor from a normal mode to a safe mode and instructs the microprocessor to invoke the software-based trap handler in the safe mode. The hardware-based FAME provides fault recovery information to the software-based trap handler via a fault recovery register (FRR) for restoring the microprocessor to a fault-free state. By utilizing a combination of the hardware-based FAME and the software-based trap handler, it is possible to effectively protect the microprocessor from malicious fault attacks without significantly increasing performance and area overheads.

A system for testing a design of a computing component includes an input device configured to receive a request to perform a test of a component, and a testing unit including a simulation of the component. The simulation is configured to output a result indicative of a response to a set of instruction addresses, the set of instruction addresses is acquired from a plurality of addresses, and the plurality of addresses including a plurality of address groups, where each address group is associated with a respective group identifier. The system also includes a plurality of requestors configured to apply the set of instruction addresses to the simulation, where a requestor of the plurality of requestors is configured to select an address for application to the simulation based on a received group identifier and a variably configurable weight value assigned to the received group identifier and the requestor.

A method includes determining, by an analysis system, a system aspect of a system for an issue recovery improvement evaluation. The method further includes determining, by the analysis system, at least one evaluation perspective and at least one evaluation viewpoint for use in performing the issue recovery improvement evaluation on the system aspect. The method further includes obtaining, by the analysis system, issue recovery improvement data regarding the system aspect in accordance with the at least one evaluation perspective and the at least one evaluation viewpoint. The method further includes calculating, by the analysis system, an issue recovery improvement rating as a measure of system issue recovery improvement maturity for the system aspect based on the issue recovery improvement data, the at least one evaluation perspective, the at least one evaluation viewpoint, and at least one evaluation rating metric.

A method includes determining, by an analysis system, a system aspect of a system for an issue recovery improvement evaluation. The method further includes determining, by the analysis system, at least one evaluation perspective and at least one evaluation viewpoint for use in performing the issue recovery improvement evaluation on the system aspect. The method further includes obtaining, by the analysis system, issue recovery improvement data regarding the system aspect in accordance with the at least one evaluation perspective and the at least one evaluation viewpoint. The method further includes calculating, by the analysis system, an issue recovery improvement rating as a measure of system issue recovery improvement maturity for the system aspect based on the issue recovery improvement data, the at least one evaluation perspective, the at least one evaluation viewpoint, and at least one evaluation rating metric.

Disclosed are systems, methods, and computer-readable media for inspecting mobile devices. In one embodiment, a method is disclosed comprising executing a de-trash operation on a mobile device, the de-trash operation resulting in the removal of extraneous material attached to the mobile device; categorizing an operating system of the mobile device; connecting the mobile device to a reading device and installing one or more software applications on the mobile device, the one or more software application operable to read one or more identifiers from the mobile device; visually inspecting the mobile device and classifying the physical condition of the mobile device; performing a functional test on the mobile device upon determining that the physical condition of the mobile device is free of defects; and removing all test data from the mobile device after performing the functional test and flashing the mobile device with a new operating system image.

A system for performing a failure assessment of an IC may comprise a hardware subsystem and a control subsystem to control operations performed by the hardware subsystem. The hardware system may change a duration of cycles of a clocking signal on the IC, and stop the clocking signal at a selected clock cycle. The operations may comprise changing the duration of selected clock cycles across a block of clock cycles, and performing a binary search across the block of clock cycles, such that the selected clock cycles are temporally placed at selected different locations within the block of clock cycles. At each iteration of the binary search, the system determines when a failure occurs. When the binary search indicates a single clock cycle causing a failure, the system stops clocking transitions at the single clock cycle, and the system extracts data from one or more circuit components of the IC.

A system for performing a failure assessment of an IC may comprise a hardware subsystem and a control subsystem to control operations performed by the hardware subsystem. The hardware system may change a duration of cycles of a clocking signal on the IC, and stop the clocking signal at a selected clock cycle. The operations may comprise changing the duration of selected clock cycles across a block of clock cycles, and performing a binary search across the block of clock cycles, such that the selected clock cycles are temporally placed at selected different locations within the block of clock cycles. At each iteration of the binary search, the system determines when a failure occurs. When the binary search indicates a single clock cycle causing a failure, the system stops clocking transitions at the single clock cycle, and the system extracts data from one or more circuit components of the IC.

Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.