A storage area allocation method for allocating a storage area with a requested allocation size area may include receiving an allocation request for a storage area that includes the requested allocation size, acquiring an available storage area whose size is a smallest size of a product of all of the product of power-of-2 sizes and the region allocation unit size encompassing the requested allocation size from the region; obtaining a binary expression whose value is the requested allocation size divided by the allocation unit size; and allocating a contiguous storage area comprised of storage areas each of whose size is a product of the allocation unit size and a power of 2 of a value of a bit position wherein a 1 is set in the binary expression and which contiguous storage area is conjoined by the storage areas in a sequence of magnitude of sizes of the storage areas.

A storage area allocation method for allocating a storage area with a requested allocation size area may include receiving an allocation request for a storage area that includes the requested allocation size, acquiring an available storage area whose size is a smallest size of a product of all of the product of power-of-2 sizes and the region allocation unit size encompassing the requested allocation size from the region; obtaining a binary expression whose value is the requested allocation size divided by the allocation unit size; and allocating a contiguous storage area comprised of storage areas each of whose size is a product of the allocation unit size and a power of 2 of a value of a bit position wherein a 1 is set in the binary expression and which contiguous storage area is conjoined by the storage areas in a sequence of magnitude of sizes of the storage areas.

A method and apparatus for creating and using cached blocks of bytecode are disclosed. An example apparatus includes a virtual machine execution engine configured to load an input variable value in conjunction with starting execution of bytecode associated with an application. The execution engine is also configured to read a cache table entry stored in a class file related to the application. The cache table entry includes a demarcation of a selected portion of the bytecode of the application that is stored within a cache block, a cache block input variable, and a cache block output variable. The execution engine is further configured to compare the loaded input variable value to the cache block input variable. Responsive to the input variable value matching the cache block input variable, the execution engine is configured to skip execution of the selected portion of the bytecode and read the cache block output variable.

Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods are disclosed. In certain aspects, memory controllers are employed that can provide memory capacity compression. In certain aspects disclosed herein, a next read address prefetching scheme can be used by a memory controller to speculatively prefetch data from system memory at another address beyond the currently accessed address. Thus, when memory data is addressed in the compressed memory, if the next read address is stored in metadata associated with the memory block at the accessed address, the memory data at the next read address can be prefetched by the memory controller to be available in case a subsequent read operation issued by a central processing unit (CPU) has been prefetched by the memory controller.

An example of the invention is a memory device including a controller and a plurality of randomly accessible memories that are capable of storing user data from a host. The controller includes data management information managing correspondence relations between address areas to be designated by the host and the plurality of memories, and compression policy management information managing associations of the address areas to be designated by the host with priorities in compressing user data to be stored in the plurality of memories. The controller is configured to determine a compression policy associated with a designated address area included in an access request from the host based on a priority associated with the designated address area and information on free space of the plurality of memories.

An example of the invention is a memory device including a controller and a plurality of randomly accessible memories that are capable of storing user data from a host. The controller includes data management information managing correspondence relations between address areas to be designated by the host and the plurality of memories, and compression policy management information managing associations of the address areas to be designated by the host with priorities in compressing user data to be stored in the plurality of memories. The controller is configured to determine a compression policy associated with a designated address area included in an access request from the host based on a priority associated with the designated address area and information on free space of the plurality of memories.

A provided a storage device configured to support a number of namespaces. The storage device includes a memory and a controller coupled to the memory. The controller includes a host interface layer and a flash translation layer configured to report to the host interface layer a first over-provisioning chunk from an over-provisioning pool and a first chunk separate from the over-provisioning pool. The controller is configured to receive a command at the host interface layer to utilize a portion of the memory for a first namespace from among the number of namespaces and the first namespace includes an unaligned chunk. The controller is configured to utilize the first over-provisioning chunk as the unaligned chunk of the first namespace. A number of over-provisioning chunks to be utilized as unaligned chunks is less than the number of namespaces.

A set of data storage values is received. It is determined that a data storage value in the set will not fit in an available memory segment including variable data column widths based at least in part on data sizes specified in a plurality of segment layout maps. A memory segment is selected for which a column width of a column will be expanded. A column width of the selected memory segment is expanded. A segment layout map corresponding to the selected memory segment is updated. The set of data storage values is stored in the selected memory segment.

A set of data storage values is received. It is determined that a data storage value in the set will not fit in an available memory segment including variable data column widths based at least in part on data sizes specified in a plurality of segment layout maps. A memory segment is selected for which a column width of a column will be expanded. A column width of the selected memory segment is expanded. A segment layout map corresponding to the selected memory segment is updated. The set of data storage values is stored in the selected memory segment.

A storage system performs garbage collection, with data compression, in storage memory. The system obtains hash results from data segments. The system determines similarity of content of data segments, based on the hash results. The system performs data compression of live data of two or more data segments that have similarity of content meeting a similarity threshold. The system writes the compressed live data of the two or more data segments into the storage memory.