A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.

The technology disclosed herein pertains to a system and method for providing the ability for a computational storage device (CSD) to understand data layout based upon automatic detection or host identification of the file system occupying a non-volatile memory express (NVMe) namespace, the method including receiving, at a CSD, a request to process a file using a computation program stored on the CSD, detecting a filesystem associated with the file within a namespace of CSD, mounting the filesystem on the CSD, interpreting a data structure associated with the file within the namespace, and reading the physical data blocks associated with the file into a computational storage memory (CSM) of the CSD.

An electronic device includes a bus driver and circuitry. The bus driver is coupled to a parallel bus including N data lines. The circuitry is configured to receive a data unit for transmission over the N data lines, to determine a first count indicative of a number of data bits in the data unit having a predefined value, and a second count indicative of a number of inverted data bits relative to corresponding bits in a previously transmitted data unit, to make a decision of whether to invert the data unit based on the first and second counts, depending on whether such inversion is expected to reduce power consumption of transmitting the data unit over the bus, to produce an output data unit by retaining or inverting the data unit based on the decision, and to transmit the output data unit over the data lines via the bus driver.

According to an embodiment of the disclosure, an electronic device comprises: a battery, a memory, a connector including one or more signal terminals, a first converter included in a first path that connects the battery to the connector, a second converter included in second path that is distinct from the first path and connects the battery to the connector, and a processor electrically connected to the battery, the memory, the connector, the first converter, and the second converter, wherein the memory stores instructions that, when executed, cause the processor to obtain identification information of the external electronic device when the electronic device is connected to the external electronic device through the connector, determine whether the identification information matches comparison data stored in the memory, determine whether a voltage of a power terminal (vbus) among the one or more signal terminals satisfies a specified condition when the identification information matches the comparison data, and transmit power determined based on a real-time voltage of the battery to the external electronic device by using the second path through the connector, based on whether the specified condition is satisfied.

An open compute project (OCP) adapter card and a computer device are disclosed. The adapter card includes an OCP connector, a controller, a selector, and a motherboard connector. The OCP connector is configured to connect to an OCP network interface card (NIC). The controller is configured for bandwidth allocation, in-situ control and power-on/off control of the OCP NIC. The selector gates a single-homed host or a dual-homed host based on working mode configuration information stored in the controller. The motherboard connector is configured to connect to a motherboard device.

A transceiver device for a user station of a serial bus system, a communication control device, and a method. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus of the bus system, a reception module for receiving the signal from the bus, the reception module being designed to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place as a result of the operating mode changeover signal.

A transceiver device, communication control device, and method for a user station of a serial bus system. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus, a reception module for receiving the signal from the bus, the reception module configured to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place based on the operating mode changeover signal. The changeover feedback block is configured to output the feedback to the communication control device via the second terminal and in the digital reception signal.

A data interface sleep and wakeup method includes receiving data information sent by a second electronic device, where the data information includes sleep information, and setting, based on the sleep information, at least one data interface to either a sleep state or a wakeup state.

Examples are described herein for dynamically allocating shared bus lanes provided by a peripheral component bridge. A multiplexor may be operably coupled with the bridge via the shared bus lanes. A plurality of peripheral component slots may each be operably coupled with the multiplexor via a respective plurality of peripheral bus lanes. The multiplexor may multiplex the shared bus lanes to multiple different peripheral component slots. Circuitry may: interrogate each of the peripheral component slots to obtain information about a modular component installed in the peripheral component slot, wherein the information about the modular component includes a usable range of bus lanes and a transmission speed capability; and cause the multiplexor to dynamically allocate the number of shared bus lanes to the respective pluralities of peripheral bus lanes of the peripheral component slots based on the usable ranges and transmission speed capabilities of the installed modular components.

A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.