The present disclosure provides a mobile power supply and a method for supplying power to a peripheral device. The mobile power supply comprises a first peripheral connection port and a second peripheral connection port, a first group of connection-port processing circuits and a second group of connection-port processing circuits, a control circuit, and a power supply circuit. A control strategy determining circuit in each group of connection-port processing circuits determines a voltage adjustment strategy according to power supply status information of a corresponding peripheral connection port. The control circuit then causes a voltage adjusting circuit in the connection-port processing circuit to adjust, according to the voltage adjustment strategy, a voltage output by the power supply circuit, such that the adjusted voltage is used to supply power to a peripheral device coupled, by means of a power supply terminal, to the peripheral connection port.

A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

Various data bus monitoring, analysis, and logging systems, devices, and methods are described herein. In one example, an apparatus includes a first circuit configured to monitor first packets among traffic carried by one or more first directional lanes of a communication link established between a host and one or more endpoint devices and determine header information for the first packets. The apparatus includes a second circuit configured to detect second packets among traffic carried by one or more second directional lanes of the communication link based at least in part on the header information determined for the first packets. The apparatus includes an analysis element configured to establish transaction metadata comprising properties of transactions on the communication link based at least on correlations among the first packets and the second packets.

Provided is a program update management device that includes: an acquiring part that acquires a scene signal indicating a scene in which a vehicle is used; a determining part that determines a level indicating how strongly the vehicle is restricted when respective functions of a plurality of ECUs are impaired, the plurality of ECUs each having the same function in the scene indicated by the scene signal; and a selecting part that selects, from among the plurality of ECUs, an ECU for which a program update is performed, based on the level.

A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.

Disclosed are embodiments that provide digital data communication between a single-pair Ethernet and a multi-pair Ethernet. Some embodiments include a single-pair Ethernet interface that is configured to operate in at least two modes. In a first mode, the single-pair Ethernet interface operates in a conventional manner. In a second mode, alternate pin configurations are employed to provide a low-cost interoperability between a single-pair Ethernet interface and a multi-pair Ethernet interface. For example, in the second mode, the single-pair Ethernet receives, via a first receive data pin, from a first transmit data pin of the multi-pair Ethernet interface, a data signal, and receives, via a second receive data pin, from a second transmit data pin of the multi-pair Ethernet interface, a second data signal.

A switched mode power supply comprises a communication interface including an address terminal configured to couple to an external resistor for setting a communication address of the switched mode power supply. A control circuit is configured to determine the value of the external resistor a first time with a first technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the first technique if the value of the external resistor is greater than the threshold value. The control circuit is also configured to, if the value of the external resistor is less than the threshold value, determine the value of the external resistor a second time with a second technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the second technique.

A switched mode power supply comprises a communication interface including an address terminal configured to couple to an external resistor for setting a communication address of the switched mode power supply. A control circuit is configured to determine the value of the external resistor a first time with a first technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the first technique if the value of the external resistor is greater than the threshold value. The control circuit is also configured to, if the value of the external resistor is less than the threshold value, determine the value of the external resistor a second time with a second technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the second technique.

A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.