A method of identifying, in a circuit design of an electronic circuit, a source of side channel leakage of the electronic circuit. The method comprises: a) simulating over a leakage time interval an operation of the circuit in response to at least one stimulus, thereby deriving for each one of the at least one stimulus per circuit part of the electronic circuit a respective simulated leakage quantity circuit part response over the leakage time interval; b) obtaining for each one of the at least one stimulus an expected leakage quantity response over the leakage time interval from a processing of each one of the at least one stimulus by a leakage model, the leakage model modelling a leak-quantity at a processing of a secure asset; c) determining respective circuit part correlations over the leakage time interval between the respective simulated leakage quantity circuit part responses and the expected leakage quantity responses; d) ranking the circuit parts based on the circuit part correlations between the respective simulated leakage quantity circuit part responses and the expected leakage quantity responses and e) identifying as the source of side channel leakage the circuit part for which a highest one of the circuit correlations has been determined between the expected leakage quantity responses and the respective simulated leakage quantity circuit part responses.

A method of identifying, in a circuit design of an electronic circuit, a source of side channel leakage of the electronic circuit. The method comprises: a) simulating over a leakage time interval an operation of the circuit in response to at least one stimulus, thereby deriving for each one of the at least one stimulus per circuit part of the electronic circuit a respective simulated leakage quantity circuit part response over the leakage time interval; b) obtaining for each one of the at least one stimulus an expected leakage quantity response over the leakage time interval from a processing of each one of the at least one stimulus by a leakage model, the leakage model modelling a leak-quantity at a processing of a secure asset; c) determining respective circuit part correlations over the leakage time interval between the respective simulated leakage quantity circuit part responses and the expected leakage quantity responses; d) ranking the circuit parts based on the circuit part correlations between the respective simulated leakage quantity circuit part responses and the expected leakage quantity responses and e) identifying as the source of side channel leakage the circuit part for which a highest one of the circuit correlations has been determined between the expected leakage quantity responses and the respective simulated leakage quantity circuit part responses.

In certain embodiments, a method for designing a semiconductor device includes generating a 2D design for fabricating chiplets on a substrate. The chiplets are component levels for a multi-chip integrated circuit. The 2D design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The first and second chiplets are adjacent on the substrate. The second layout is a mirror image of the first layout across a reference line shared by the first and second chiplets. The first surfaces of the first and second chiplets are both either top or bottom surfaces. The method further includes generating one or more photomasks according to the design.

In certain embodiments, a method for designing a semiconductor device includes generating a 2D design for fabricating chiplets on a substrate. The chiplets are component levels for a multi-chip integrated circuit. The 2D design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The first and second chiplets are adjacent on the substrate. The second layout is a mirror image of the first layout across a reference line shared by the first and second chiplets. The first surfaces of the first and second chiplets are both either top or bottom surfaces. The method further includes generating one or more photomasks according to the design.

Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.

A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.

A system design support apparatus generates new user data on the basis of derived user data including: base user data reference information that is information specifying user data to be referred to; and information on an item changed from the user data specified by the base user data reference information and on changed contents. A system design support method includes a step of selecting user data to be used, a step of generating derived user data including: base user data reference information for specifying the selected user data to be used; and information on an item changed from the user data specified by the base user data reference information and on changed contents, and a step of generating new user data on the basis of the derived user data.

A system design support apparatus generates new user data on the basis of derived user data including: base user data reference information that is information specifying user data to be referred to; and information on an item changed from the user data specified by the base user data reference information and on changed contents. A system design support method includes a step of selecting user data to be used, a step of generating derived user data including: base user data reference information for specifying the selected user data to be used; and information on an item changed from the user data specified by the base user data reference information and on changed contents, and a step of generating new user data on the basis of the derived user data.