Patent classifications
G06F30/31
Electronic device, method for generating package drawing and computer readable storage medium
The present disclosure provides an electronic device, a method for generating a package drawing, and a computer readable storage medium. The electronic device includes a display device and a processor, the processor is configured to obtain a type of the element and size parameters corresponding to the element input by a user; determine a size and a position of each of pads corresponding to the element according to the type of the element and the size parameters corresponding to the element, and draw the pads; determine coordinates of endpoints of an entity layer corresponding to the element, and draw the entity layer; determine coordinates of endpoints of a height layer corresponding to the element, and draw the height layer; and determine coordinates of endpoints of a screen layer corresponding to the element, and draw the screen layer.
Electronic device, method for generating package drawing and computer readable storage medium
The present disclosure provides an electronic device, a method for generating a package drawing, and a computer readable storage medium. The electronic device includes a display device and a processor, the processor is configured to obtain a type of the element and size parameters corresponding to the element input by a user; determine a size and a position of each of pads corresponding to the element according to the type of the element and the size parameters corresponding to the element, and draw the pads; determine coordinates of endpoints of an entity layer corresponding to the element, and draw the entity layer; determine coordinates of endpoints of a height layer corresponding to the element, and draw the height layer; and determine coordinates of endpoints of a screen layer corresponding to the element, and draw the screen layer.
WORK SUPPORT DEVICE, WORK SUPPORT SYSTEM, AND ANALYSIS PROGRAM
A work support device according to the invention detects circuit symbols and conducting wires from circuit drawing data that does not have information unique to a circuit part, and by matching the detection result with a result of tracing a conduction path by handwriting by a worker, the circuit part and the conducting wire through which the conduction path passes are specified.
WORK SUPPORT DEVICE, WORK SUPPORT SYSTEM, AND ANALYSIS PROGRAM
A work support device according to the invention detects circuit symbols and conducting wires from circuit drawing data that does not have information unique to a circuit part, and by matching the detection result with a result of tracing a conduction path by handwriting by a worker, the circuit part and the conducting wire through which the conduction path passes are specified.
Integrated circuit device design method and system
A method of designing an integrated circuit (IC) device includes identifying, using a processor, data corresponding to an IC manufacturing process. The designing also includes assigning, using the processor, the data to one or more design rule instruction macros. The designing also includes selecting, using the processor, one or more constraints to be applied to the one or more design rule instruction macros. The designing also includes executing, using the processor, the one or more design rule instruction macros to configure a design rule for the IC manufacturing process.
Integrated circuit device design method and system
A method of designing an integrated circuit (IC) device includes identifying, using a processor, data corresponding to an IC manufacturing process. The designing also includes assigning, using the processor, the data to one or more design rule instruction macros. The designing also includes selecting, using the processor, one or more constraints to be applied to the one or more design rule instruction macros. The designing also includes executing, using the processor, the one or more design rule instruction macros to configure a design rule for the IC manufacturing process.
Modular Compilation Flows for a Programmable Logic Device
Systems or methods of the present disclosure may provide an electronic device that includes memory storing instructions; and a processor, that when executing the instructions, is to receive a design for a programmable fabric of an integrated circuit device. The instructions are also to cause the processor to cause compilation of the design into a configuration during a compilation window. The instructions further are to cause the processor to determine at least some routing for the configuration outside of the compilation window.
Modular Compilation Flows for a Programmable Logic Device
Systems or methods of the present disclosure may provide an electronic device that includes memory storing instructions; and a processor, that when executing the instructions, is to receive a design for a programmable fabric of an integrated circuit device. The instructions are also to cause the processor to cause compilation of the design into a configuration during a compilation window. The instructions further are to cause the processor to determine at least some routing for the configuration outside of the compilation window.
INTERACTIVELY PRESENTING FOR MINIMUM OVERLAP SHAPES IN AN IC DESIGN
Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.
INTERACTIVELY PRESENTING FOR MINIMUM OVERLAP SHAPES IN AN IC DESIGN
Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.