G06F30/31

System and method for generating and using a context block based on system parameters
11573822 · 2023-02-07 · ·

A system and method for generating a context block using system parameters. The system parameters include objective parameters, functionality parameters, and interface definitions. Context field definitions are received. The system parameters and context fields definitions may be used to determine context fields and context entries. The system parameters may be used to determine context fields and number of context entries. The context module hardware description may be created using context fields, number of context entries, and context field definitions.

System and method for generating and using a context block based on system parameters
11573822 · 2023-02-07 · ·

A system and method for generating a context block using system parameters. The system parameters include objective parameters, functionality parameters, and interface definitions. Context field definitions are received. The system parameters and context fields definitions may be used to determine context fields and context entries. The system parameters may be used to determine context fields and number of context entries. The context module hardware description may be created using context fields, number of context entries, and context field definitions.

Method And Process Using Fingerprint Based Semiconductor Manufacturing Process Fault Detection
20230102438 · 2023-03-30 ·

Sensitivity calculations are provided of a process model through the rate of change of a model fingerprint with respect to process variables and defects. A fingerprint sensitivity table is generated, where process variables are associated with a set of fingerprint sensitivities. The fingerprint of incoming substrates is monitored through a production process by applying the same fingerprint method that is used in the process model. Calculations are made of the difference between the incoming substrate fingerprint and the process model predicted fingerprint. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable most likely to be responsible for the difference. Spatial relationships between process variables and actual measurements on the substrate may be obtained. Correlation through fingerprint sensitivity improves the ability to pinpoint faulty process tools. The difference fingerprint may also identify the formation of defects on a substrate.

Method And Process Using Fingerprint Based Semiconductor Manufacturing Process Fault Detection
20230102438 · 2023-03-30 ·

Sensitivity calculations are provided of a process model through the rate of change of a model fingerprint with respect to process variables and defects. A fingerprint sensitivity table is generated, where process variables are associated with a set of fingerprint sensitivities. The fingerprint of incoming substrates is monitored through a production process by applying the same fingerprint method that is used in the process model. Calculations are made of the difference between the incoming substrate fingerprint and the process model predicted fingerprint. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable most likely to be responsible for the difference. Spatial relationships between process variables and actual measurements on the substrate may be obtained. Correlation through fingerprint sensitivity improves the ability to pinpoint faulty process tools. The difference fingerprint may also identify the formation of defects on a substrate.

SIMULATION METHOD AND SYSTEM OF VERIFYING OPERATION OF SEMICONDUCTOR MEMORY DEVICE OF MEMORY MODULE AT DESIGN LEVEL
20230097405 · 2023-03-30 ·

A simulation method and system of verifying an operation of a semiconductor memory device of a memory module at a design level. The simulation method includes setting a configuration and an arrangement of a registered clock driver (RCD) and a configuration and an arrangement of first semiconductor memory devices to fourth semiconductor memory devices, on a printed circuit board (PCB) through a graphic user interface (GUI). When a RCD test execution command is applied through the GUI, executing a test program to apply control signals to control signal terminals of the PCB based on a command truth table, to compare the applied control signals and control signals output through first driver output terminals of the RCD, and to create an RCD test result. When the RCD operates normally, performing a test on the memory module.

SIMULATION METHOD AND SYSTEM OF VERIFYING OPERATION OF SEMICONDUCTOR MEMORY DEVICE OF MEMORY MODULE AT DESIGN LEVEL
20230097405 · 2023-03-30 ·

A simulation method and system of verifying an operation of a semiconductor memory device of a memory module at a design level. The simulation method includes setting a configuration and an arrangement of a registered clock driver (RCD) and a configuration and an arrangement of first semiconductor memory devices to fourth semiconductor memory devices, on a printed circuit board (PCB) through a graphic user interface (GUI). When a RCD test execution command is applied through the GUI, executing a test program to apply control signals to control signal terminals of the PCB based on a command truth table, to compare the applied control signals and control signals output through first driver output terminals of the RCD, and to create an RCD test result. When the RCD operates normally, performing a test on the memory module.

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, USE METHOD OF INFORMATION PROCESSING APPARATUS, USER TERMINAL, AND PROGRAM THEREFOR
20230035673 · 2023-02-02 · ·

According to this invention, it is possible to reduce the load of the user in a work of operating a model described in a hardware description language, and allow the user to readily make a change. This invention provides an information processing apparatus including a hardware processor that emulates, by hardware, operations corresponding to a model described in a hardware description language, and a control unit that controls, in accordance with instructions of a user received from a user terminal, at least one of inputs to the hardware processor and outputs from the hardware processor.

METHODS AND SYSTEMS FOR PRINTED CIRCUIT BOARD COMPONENT PLACEMENT AND APPROVAL
20230102019 · 2023-03-30 · ·

An aspect of the disclosed embodiments is a method for printed circuit board (PCB) component placement comprising: graphically displaying, on a display device, PCB design features of a PCB design; and providing a user interface control for designating one or more of the PCB design features as electrical contacts for a first selected electrical component. Other aspects are disclosed.

Tool bridge

Disclosed herein are systems and methods for sharing and synchronizing virtual content. A method may include receiving, from a host application via a wearable device comprising a transmissive display, a first data package comprising first data; identifying virtual content based on the first data; presenting a view of the virtual content via the transmissive display; receiving, via the wearable device, first user input directed at the virtual content; generating second data based on the first data and the first user input; sending, to the host application via the wearable device, a second data package comprising the second data, wherein the host application is configured to execute via one or more processors of a computer system remote to the wearable device and in communication with the wearable device.

AUTOMATED TIMING CLOSURE ON CIRCUIT DESIGNS

Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.