A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.

A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.

Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

A system, method, apparatus and integrated circuit are provided for collecting runtime performance data with a set of hardware timers under control of a dedicated hardware control register by connecting a central processing unit (CPU) and memory to a timer block bank having a plurality of timer instances which are selectively enabled and activated to collect runtime performance data during execution of application code by measuring specified software execution events, where the dedicated hardware control register includes a plurality of register fields for independently controlling activation behavior of the plurality of timer instances in response to a single write operation to all register fields in the hardware control register.

A system, method, apparatus and integrated circuit are provided for collecting runtime performance data with a set of hardware timers under control of a dedicated hardware control register by connecting a central processing unit (CPU) and memory to a timer block bank having a plurality of timer instances which are selectively enabled and activated to collect runtime performance data during execution of application code by measuring specified software execution events, where the dedicated hardware control register includes a plurality of register fields for independently controlling activation behavior of the plurality of timer instances in response to a single write operation to all register fields in the hardware control register.

Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.