A method for designing a logic circuit includes providing an initial design of the logic circuit, including at least first and second logic stages, and a sequential component, which is inserted between the first and second logic stages and comprises a flip-flop or a latch. Timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed, are estimated. Based on the timing delays, a decision is made whether the paths in which the sequential component is bypassed meet a timing constraint set for the logic circuit. A final design of the logic circuit is then generated, in which the sequential component is either bypassed or not bypassed, depending on the decision.

Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.

Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.

A method and apparatus for adaptive voltage scaling to eliminate delay variation of a whole design are provided. The method may include: reading a circuit simulation netlist file, a circuit design database, and a path list; building a delay variation database of each minimum unit within multiple minimum units of the whole design under various voltage levels according to the circuit design database; utilizing an initial voltage level to be a voltage level of a driving voltage of the whole design to apply the initial voltage level to the whole design, and performing static timing analysis (STA) on the whole design, to determine whether any timing violation path exists in the path list; and selectively adjusting the voltage level of the driving voltage and re-performing the STA until no timing violation path exists.

An optimum stage number calculation method executed by a processor, the optimum stage number calculation method includes extracting information on a signal path between a transmission cell and a reception cell that transmits and receives a signal according to a clock from net information indicating a connection relationship between a plurality of cells arranged and wired in a field programmable gate array, estimating a cell total delay amount indicating a total delay amount of cells allowed to be included in one period of the clock in the signal path from input information including at least clock period information indicating a length of one period of the clock, calculating the number of stages of logic cells included in the signal path from the cell total delay amount, and outputting number-of-stages information indicating the calculated number of stages of the logic cells.

A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

A clock distribution component may include a plurality of electrically connected buffer pair triads arranged in a plurality of levels. A buffer pair triad, of the plurality of buffer pair triads, may include three buffer pairs that are connected via wire. Each buffer pair triad may share at least one buffer pair with one or more buffer triads of the plurality of buffer pair triads. Buffer pairs, of the plurality of buffer pair triads, may be arranged in buffer rows and buffer columns. The plurality of levels may include a first level associated with a first buffer pair triad and one or more additional levels. Each level of the one or more additional levels may include at least three buffer pair triads and at least two more buffer pair triads and/or at least two less buffer pair triads than an adjacent level of the one or more additional levels.

Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

Systems and integrated circuits are provided herein. In one aspect, an integrated circuit comprises: a plurality of connection nodes comprising at least a first and second connection node; a secure IP block and a decrypt IP block coupled to the first and second connection nodes, respectively. The secure IP block is configured to: receive a data object via the first connection node, disassemble the data object into a plurality of data fragments, encrypt the plurality of data fragments, and send the plurality of encrypted data fragments to a plurality of storage locations. The decrypt IP block is configured to: receive an electrical signal indicative of a request to access a data object via the second connection node, retrieve a plurality of encrypted data fragments stored at a plurality of storage locations, decrypt the plurality of encrypted data fragments, and reassemble the decrypted data fragments into the data object.

Systems and methods for accessing a first data object are provided. In an aspect, the method comprises: receiving, by a server from a plurality of client devices, a plurality of requests to retrieve a first data object, each client device operated by a user of a plurality of users; generating a plurality of unique data objects based on the requested first data object, each unique data object associated with the first data object and associated with a user of the plurality of users; and for each client device of the plurality of client devices, providing the client device access to a respective unique data object of the plurality unique data objects based on a respective user corresponding to the client device and associated with the respective unique data object.