A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

An information processing apparatus specifies a first pattern indicating a first layer included in first circuit data. The information processing apparatus generates, based on first wiring included in a second pattern indicating a second layer that is adjacent to the first layer and a slit included in the first pattern, second circuit data by changing the first pattern to a third pattern including second wiring corresponding to the first wiring. The information processing apparatus generates, based on the second circuit data, training data for machine learning.

A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a representation of said electronic design comprised at least in part of at least one analog portion, at least one specification of said electronic design, at least one manufacturing process variation of said at least one analog portion of said electronic design and at least one functional variation of said at least one analog portion of said electronic design. At least one set of valid states delimited by one of said at least one specification, said at least one manufacturing process variation and said at least one functional variation is then generated.

A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a representation of said electronic design comprised at least in part of at least one analog portion, at least one specification of said electronic design, at least one manufacturing process variation of said at least one analog portion of said electronic design and at least one functional variation of said at least one analog portion of said electronic design. At least one set of valid states delimited by one of said at least one specification, said at least one manufacturing process variation and said at least one functional variation is then generated.

Embodiments of the present application provide a circuit simulation method and a device. The method includes: determining a top-layer structure and a minimum circuit cell layer of a circuit schematics; determining, in a circuit layout, an area and a relative distribution location of each target circuit cell in the minimum circuit cell layer; generating a first circuit structure based on the top-layer structure, each target circuit cell, and the area and the relative distribution location of each target circuit cell in the circuit layout; and adding a parasitic effect circuit to the first circuit structure, generating a target circuit structure corresponding to the circuit schematics, and performing simulation based on the target circuit structure.

Embodiments of the present application provide a circuit simulation method and a device. The method includes: determining a top-layer structure and a minimum circuit cell layer of a circuit schematics; determining, in a circuit layout, an area and a relative distribution location of each target circuit cell in the minimum circuit cell layer; generating a first circuit structure based on the top-layer structure, each target circuit cell, and the area and the relative distribution location of each target circuit cell in the circuit layout; and adding a parasitic effect circuit to the first circuit structure, generating a target circuit structure corresponding to the circuit schematics, and performing simulation based on the target circuit structure.

An analogue circuit design apparatus is disclosed comprising a primary design unit and a plurality of secondary design units. The primary design unit is configured to: receive information representing technical requirements for the analogue circuit; identify, based on the received information, a plurality of circuit portions for forming the analogue circuit; determine, for each circuit portion of the plurality circuit portions, respective technical criteria for that circuit portion; produce a set of designs comprising a respective design for each circuit portion; for at least one circuit portion of the plurality of circuit portions obtain information relating to parasitics that will be experienced in the analogue circuit if the analogue circuit were to include that designed circuit portion; adapt the design of at least one circuit portion based on the obtained information relating to parasitics; and output a complete circuit design including at least one circuit portion adapted based on obtained information relating to parasitics.

An analogue circuit design apparatus is disclosed comprising a primary design unit and a plurality of secondary design units. The primary design unit is configured to: identify a plurality of circuit portions for forming the analogue circuit; determine for each circuit portion respective technical criteria; and provide the respective technical criteria to at least one of a plurality of secondary design units. Each of the plurality of secondary design units is configured to: design a respective circuit portion based on the technical criteria for that respective circuit portion; and output a resulting initial design of the respective circuit portion. After at least an initial design of a given circuit portion has been completed by at least another one of the secondary design units, at least one of the secondary design units is configured to adapt its output initial design based on a context of its corresponding circuit portion.

An analogue circuit design apparatus is disclosed comprising a primary design unit and a plurality of secondary design units. The primary design unit is configured to: identify a plurality of circuit portions for forming the analogue circuit; determine for each circuit portion respective technical criteria; and provide the respective technical criteria to at least one of a plurality of secondary design units. Each of the plurality of secondary design units is configured to: design a respective circuit portion based on the technical criteria for that respective circuit portion; and output a resulting initial design of the respective circuit portion. The primary design unit is further configured to obtain, a set of designs comprising a respective design for each circuit portion, generate, at least an initial design for the analogue circuit, based on the set of designs, simulate an analogue circuit based on the generated design and verify whether or not the analogue circuit meets the technical requirements for the analogue circuit.