An impedance matching method includes following operations: providing load impedance data of a network interface controller chip; providing characteristic data of a network transformer, in which the network transformer is configured to be connected to the network interface controller chip via a transmission line on a printed circuit board, and a first predetermined data rate of the network transformer is lower than a second predetermined data rate of the network interface controller chip; adjusting an arrangement among the load impedance data, a length of the transmission line, and a width of the transmission line according to the characteristic data to adjust an impedance matching between the network transformer and the network interface controller chip, in order to make the network transformer meet a predetermined requirement corresponding to the second predetermined data rate; and storing the arrangement to be design data for fabricating the printed circuit board.

An impedance matching method includes following operations: providing load impedance data of a network interface controller chip; providing characteristic data of a network transformer, in which the network transformer is configured to be connected to the network interface controller chip via a transmission line on a printed circuit board, and a first predetermined data rate of the network transformer is lower than a second predetermined data rate of the network interface controller chip; adjusting an arrangement among the load impedance data, a length of the transmission line, and a width of the transmission line according to the characteristic data to adjust an impedance matching between the network transformer and the network interface controller chip, in order to make the network transformer meet a predetermined requirement corresponding to the second predetermined data rate; and storing the arrangement to be design data for fabricating the printed circuit board.

A computer-implemented method for programming an integrated circuit includes receiving a program design and determining one or more addition operations based on the program design. The method also includes performing geometric synthesis based on the one or more addition operations by determining a plurality of bits associated with the one or more addition operations and defining a plurality of counters that includes the plurality of bits. Furthermore, the method includes generating instructions configured to cause circuitry configured to perform the one or more addition operations to be implemented on the integrated circuit based on the plurality of counters. The circuitry includes first adder circuitry configured to add a portion of the plurality of bits and produce a carry-out value. The circuitry also includes second adder circuitry configured to determine a sum of a second portion of the plurality of bits and the carry-out value.

A computer-implemented method for programming an integrated circuit includes receiving a program design and determining one or more addition operations based on the program design. The method also includes performing geometric synthesis based on the one or more addition operations by determining a plurality of bits associated with the one or more addition operations and defining a plurality of counters that includes the plurality of bits. Furthermore, the method includes generating instructions configured to cause circuitry configured to perform the one or more addition operations to be implemented on the integrated circuit based on the plurality of counters. The circuitry includes first adder circuitry configured to add a portion of the plurality of bits and produce a carry-out value. The circuitry also includes second adder circuitry configured to determine a sum of a second portion of the plurality of bits and the carry-out value.

Systems or methods of the present disclosure may provide for determining a load line for operation of a programmable logic fabric where the load line is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The load line may be determined using software modeling for the design or configuration. Additionally or alternatively, the load line may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

A method is provided to design a filter. In the method, a difference between a high frequency to be blocked and a resonance frequency of a distributed constant type reference filter is obtained, the reference filter including a reference coil having windings wound at a plurality of pitches having the same length in an axial direction and a capacitor connected in parallel to the reference coil. When the difference is greater than the predetermined value, a split position in the reference coil where the reference coil is divided into a first coil element and a second coil element connected in series and a split distance between the first coil element and the second coil element to reduce the first difference.

An integrated-circuit design tool system capable of minimizing a plasma induced charging effect to a transistor in a plasma-based process performed for a dielectric layer on a metal layer comprises a pre-processing unit, a charging evaluator engine, a charging eliminator engine, a post-processing unit, and a non-transitory computer readable medium.

Disclosed is an approach to implement a requirements-driven analog verification flow. Disparate islands of verification tasks are performed with individual cellviews to be set into an overarching and closed loop verification flow context for a project or a complex verification task.

Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.

Embodiments of the present invention may provide the capability to design SRAM cells may be designed that is compatible with the requirements of InGaAs integration by selective epitaxy in SiO.sub.2 cavities without sacrificing density and area scaling. In an embodiment of the present invention, a computer-implemented method for designing a hybrid integrated circuit may comprise receiving data representing a layout of a static random-access memory cell array, identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array, selecting from among the identified areas at least one area, expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area, and marking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region.