Aspects of the disclosed technology relate to techniques of activity coverage assessment. Transistor-level circuit simulation is performed for a circuit design under a set of test stimuli, which determines values of one or more electrical properties for each of circuit elements of interest in the circuit design. The one or more electrical properties are selected based on information of the each of circuit elements of interest, which comprises what circuit element type the each of circuit elements of interest belongs to. Based on the values of the one or more electrical properties, activity coverage information comprising information about which circuit elements in the circuit elements of interest are active or inactive under the set of test stimuli is determined.

A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios. Further, the method comprises generating, with a processor and for the first sampling size, a confidence score for each of the plurality of bins based on the error value for each of the plurality of coverage scenarios, and outputting the confidence score for each of the plurality of bins.

A system displays a visual representation of the operation of an electronic circuit. The position of graphical elements representing values of signals in the circuit convey information about the operation of the circuit. The visual representation may further depict navigable levels of hierarchy of the electronic circuit.

This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.

A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios. Further, the method comprises generating, with a processor and for the first sampling size, a confidence score for each of the plurality of bins based on the error value for each of the plurality of coverage scenarios, and outputting the confidence score for each of the plurality of bins.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

A system for mapping a neural network architecture onto a computing core and a method of mapping a neural network architecture onto a computing core may be provided, the system comprises a neural network module configured to provide a neural network; a data input module coupled to the neural network module, the neural network module configured to provide input data to the neural network; a layer selector module coupled to the neural network module, the layer selector module configured to select a layer of the neural network; a pipeline module coupled to the layer selection module, the pipeline module configured to perform at least one backward pipelining analysis from the selected layer of the layer selector module, the pipeline module being arranged to perform the at least one backward pipelining analysis towards an input layer of the neural network; a mapper module coupled to the pipeline module, the mapper module being arranged to receive activation information from the pipeline module, the activation information based on the at least one backward pipelining analysis; and wherein the mapper module is further arranged to map at least the selected layer of the neural network using the activation information to a computing core.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.