A work support device according to the invention detects circuit symbols and conducting wires from circuit drawing data that does not have information unique to a circuit part, and by matching the detection result with a result of tracing a conduction path by handwriting by a worker, the circuit part and the conducting wire through which the conduction path passes are specified.

A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.

A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.

An assembling method for a multi-core cable having a plurality of electrical insulated wires is designed to connect one-end-portions of the electrical insulated wires to electrode patterns, respectively, of one circuit board, correspondingly connect other-end-portions of the electrical insulated wires to electrode patterns, respectively, of the other circuit board, compute intersection coefficients on one end side and the other of the cable, and iterate interchanging connecting destinations for the one-end-portions of the electrical insulated wires, correspondingly interchanging connecting destinations for the other-end-portions of the electrical insulated wires, and computing the intersection coefficients on the one end side and the other of the cable. The connecting destinations for the electrical insulated wires to the electrode patterns are determined in such a manner that a maximum intersection coefficient denoting either larger one of the respective intersection coefficients of the one end side and the other of the cable is made small.

Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

Boundary cells are used to abut two standard cell blocks. A standard cell block for an integrated circuit device includes a first standard cell, and a first boundary cell disposed adjacent to the first standard cell and along a boundary of the standard cell block. The first boundary cell includes a first region, a first dummy region, and a first layer extension region. The first region is abutted with the first standard cell and the first dummy region. The first dummy region is abutted with the first layer extension region. The first region and the first dummy region each include one or more non-functional layers. The first region, the first dummy region, and the first layer extension region are of a first semiconductor type.

Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a first voltage supply having the first supply voltage.

A method for obtaining board parameters of a printed circuit board, including the following steps: obtaining parameter information of a stripline on the printed circuit board; obtaining physical parameters of the stripline based on the parameter information of the stripline and a predetermined electromagnetic simulation application; calculating required board parameters of the printed circuit board based on the parameter information and the physical parameters of the stripline. In the present disclosure, the physical parameters of the stripline are obtained based on the physical nature of the stripline on the printed circuit board, and there is no need for fitting or adopting a hypothetical model in order to obtain board parameters corresponding to each frequency point of the stripline; the present disclosure is simple and straightforward during operation, and the obtained board parameters of the printed circuit board are highly accurate.