The invention provides an apparatus comprising a programmable circuit including a plurality of 2-input 1-output ALUs, and an updating unit updating the programmable circuit according to circuit information, wherein each of the ALUs includes a calculation unit which performs a set type of calculation for two data and output a calculation result, a delay unit which delays the two input data in accordance with delay amounts independently set and supplies the delayed data to the calculation unit, and a controller which controls a delay amount for the delay unit and a calculation timing for the calculation unit in accordance with externally set information, wherein the updating unit sets clock gating start timings for a plurality of delay elements of the delay unit if an ALU of interest as a first processing circuit in the programmable circuit inputs final data to be processed.

The invention provides an apparatus comprising a programmable circuit including a plurality of 2-input 1-output ALUs, and an updating unit updating the programmable circuit according to circuit information, wherein each of the ALUs includes a calculation unit which performs a set type of calculation for two data and output a calculation result, a delay unit which delays the two input data in accordance with delay amounts independently set and supplies the delayed data to the calculation unit, and a controller which controls a delay amount for the delay unit and a calculation timing for the calculation unit in accordance with externally set information, wherein the updating unit sets clock gating start timings for a plurality of delay elements of the delay unit if an ALU of interest as a first processing circuit in the programmable circuit inputs final data to he processed,