A method for generating M parallel pseudorandom binary sequences (PRBSs), each comprising a 2.sup.n1 sequence of pseudorandom bits, includes loading into the circuit an initial M-bit word, the initial M-bit word comprising M sequential bits selected from a pre-determined PRBS-n sequence, wherein n>1 and M>n. The method includes generating, using a plurality of logic gates of the circuit, a next M-bit word using at least n+1 of the M sequential bits of the initial M-bit word. The method includes repeatedly generating, using the logic gates of the circuit, the next M-bit word from a previous M-bit word using the at least n+1 of M sequential bits of the previous M-bit word, resulting in M parallel sequences of the PRBS-n sequence. The method includes transmitting the generated next M-bit words on an M-bit wide parallel bus.

Unpredictable random numbers are used to provide the parameter values and seeds for a parameterized random number generator, thereby providing forensic reproducibility of a simulation. The values generated unpredictably to provide the parameters and seeds for the random number generator are stored so that the same random numbers can be utilized for a subsequent computation in the simulation.

A method for generating M parallel pseudorandom binary sequences (PRBSs), each comprising a 2.sup.n1 sequence of pseudorandom bits, includes loading into the circuit an initial M-bit word, the initial M-bit word comprising M sequential bits selected from a pre-determined PRBS-n sequence, wherein n>1 and M>n. The method includes generating, using a plurality of logic gates of the circuit, a next M-bit word using at least n+1 of the M sequential bits of the initial M-bit word. The method includes repeatedly generating, using the logic gates of the circuit, the next M-bit word from a previous M-bit word using the at least n+1 of M sequential bits of the previous M-bit word, resulting in M parallel sequences of the PRBS-n sequence. The method includes transmitting the generated next M-bit words on an M-bit wide parallel bus.

The invention relates to a stochastic-type microprocessor. In some embodiments, the microprocessor comprises an elementary stochastic computation module able to receive, as input, two random and independent binary input signals each representing a binary coding of two respective given input probability values, and able to generate, as output, a random binary output signal. The elementary module comprises: a programmable logic unit, able to combine two input signals to generate an output signal; an addressable memory, able to store an output probability value coded by an output signal generated by the logic unit; a first stochastic clock, able to produce a first clock signal; a second stochastic clock, able to produce a second clock signal.

A method for realization of samples of random numbers distributed on temporal and spatial lattice points is described. The method may include using samples obtained by integrating a temporal and spatial white noise over the temporally smallest unit and over the spatial unit of volume, with the distribution of samples. The method may ensure small correlations to neighboring samples in temporal as well as spatial directions.

The invention relates to a stochastic-type microprocessor.

In some embodiments, the microprocessor comprises an elementary stochastic computation module able to receive, as input, two random and independent binary input signals each representing a binary coding of two respective given input probability values, and able to generate, as output, a random binary output signal.

The elementary module comprises: a programmable logic unit, able to combine two input signals to generate an output signal; an addressable memory, able to store an output probability value coded by an output signal generated by the logic unit; a first stochastic clock, able to produce a first clock signal; a second stochastic clock, able to produce a second clock signal.

A bit sequence generator for generating a bit sequence defined by a generating function and an initial state of the generating function comprising a plurality of state machines and a multiplexer. Each state machine of the plurality of state machines generates a time-interleaved bit sequence, wherein a state machine generates a bit of the time-interleaved bit sequence for a current time step based on at least one bit generated by the state machine for a preceding time step, the generating function of the bit sequence to be generated, and the initial state of the generating function and independent from a time-interleaved bit sequence generated by another state machine of the plurality of state machines. Further, a multiplexer selects successively one bit from each generated time-interleaved bit sequence in a repetitive manner to obtain the bit sequence defined by the generating function and the initial state of the generating function.