This control system includes: a first arithmetic unit for doing cyclic execution of a first task to which one or a plurality of processes are allocated using a first control cycle; and a second arithmetic unit for doing cyclic execution of a second task to which one or a plurality of processes are allocated using a second control cycle that is longer than the first control cycle. For the first task, a first data collection process with a first input data as the target and a corresponding first data processing process are allocated. Depending on the setting via the support device, a second data collection process with a second input data as the target and a corresponding second data processing process are allocated to either of the first task and the second task.

A task manager tightly coupled to a programmable real-time unit (PRU), the task manager configured to: detect a first event; assert, a request to the PRU during a first clock cycle that the PRU perform a second task; receive an acknowledgement of the request from the PRU during the first clock cycle; save a first address in a memory during the first clock cycle of the PRU, the first address corresponding to a first task of the PRU, the first address present in a current program counter of the PRU; load a second address of the memory into a second program counter during the first clock cycle, the second address corresponding to the second task; and load, during a second clock cycle, the second address into the current program counter, wherein the second clock cycle immediately follows the first clock cycle.

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

According to one aspect of the present disclosure, a technique for job distribution within a grid environment includes receiving jobs at a submission cluster for distribution of the jobs to one or more execution clusters where each of the execution clusters has one or more execution hosts and maintains a pending job queue. A resource capacity corresponding to each respective execution cluster is determined, and resource requirements for the jobs is determined. A length of the pending job queue indicating a quantity of pending jobs to maintain in the pending job queue for the respective execution cluster is dynamically calculated and periodically adjusted based on the resource capacity and the resource requirements of the respective execution clusters. The jobs are allocated to the respective execution clusters according to the length of the pending job queue of the respective execution clusters.

A task manager tightly coupled to a programmable real-time unit (PRU), the task manager configured to: detect a first event; assert, a request to the PRU during a first clock cycle that the PRU perform a second task; receive an acknowledgement of the request from the PRU during the first clock cycle; save a first address in a memory during the first clock cycle of the PRU, the first address corresponding to a first task of the PRU, the first address present in a current program counter of the PRU; load a second address of the memory into a second program counter during the first clock cycle, the second address corresponding to the second task; and load, during a second clock cycle, the second address into the current program counter, wherein the second clock cycle immediately follows the first clock cycle.

A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

A method, computer program product, and computing system for allocating a first set of cores of a plurality of cores of a multicore central processing unit (CPU) for processing host input-output (IO) operations of a plurality of operations on a storage system. A second set of cores of the plurality of cores may be allocated for processing flush operations of the plurality of operations on the storage system. A third set of cores of the plurality of cores may be allocated for processing rebuild operations of the plurality of operations on the storage system. At least one of one or more host TO operations, one or more rebuild operations, and one or more flush operations may be processed, via the plurality of cores and based upon, at least in part, the allocation of the plurality of cores for processing the plurality of operations.

A method, system, and computer program for processing records is disclosed. In some aspects, a method includes associating, on at least one of the plurality of processors, each record with a record set of a plurality of record sets. Each record set is assigned to a sub-database based on the record set. A cache is associated with each sub-database, and each sub-database and its associated cache is associated with a processor set. An affinity is created between each database cache and the associated processor set, and records are processed with the processor sets according to the associations.

Reconfiguring processing groups for cascading data workloads including receiving a request to reconfigure a computing system to execute a workload, wherein the computing system comprises a first processing group and a second processing group, wherein the first processing group comprises a first central processing unit (CPU), a first graphics processing unit (GPU), and a second GPU, and wherein the second processing group comprises a second CPU and a third GPU; reconfiguring the computing system including activating a processor link spanning the first processor group and the second processor group between the second GPU and the third GPU; and executing the workload using the first GPU, second GPU, and third GPU including cascading data, via processor links, from the first CPU to the first GPU, from the first GPU to the second GPU, and from the second GPU to the third GPU.

An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a host controller, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.