A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

A reconfigurable data processor comprises an array of configurable units configurable to allocate a plurality of sets of configurable units in the array to implement respective execution fragments of the data processing operation. Quiesce logic is coupled to configurable units in the array, configurable to respond to a quiesce control signal to quiesce the sets of configurable units in the array on quiesce boundaries of the respective execution fragments, and to forward quiesce ready signals for the respective execution fragments when the corresponding sets of processing units are ready. An array quiesce controller distributes the quiesce control signal to configurable units in the array, and receives quiesce ready signals for the respective execution fragments from the quiesce logic.

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

A method uses an explicit resource file (ERF) to repetitively execute a set of processes using consistent resources. The method generates the ERF for a set of processes. The ERF identifies one or more specified central processing units (CPUs), one or more specified graphics processing units (GPUs), and one or more memory ranges in memory to be used by the one or more specified CPUs and the one or more specified GPUs when executing the set of processes. The method enforces compliance with the ERF when repetitively executing the set of processes.

A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

A computer-implemented method and system for affinity based optimization of persistent memory volumes. Responsive to receiving a request for a parent virtual PMEM device, a total memory capacity is apportioned amongst virtual persistent memory (PMEM) resources and physical memory resources. In accordance with a target affinity characteristic, a set of virtual central processor unit (CPU) sockets are assigned. Each virtual CPU socket is configured based on at least one physical central processor unit (CPU) core in conjunction with a subset of the virtual PMEM and physical memory resources. Child virtual PMEM devices are created for respective ones of the virtual CPU sockets, each of the child virtual PMEM devices being dedicated to the parent virtual PMEM device.

Embodiments of the present application provide a task allocation method and system. The method includes: analyzing at least one query pattern of a target task to acquire expected response time of the query pattern; estimating system cost information and estimated response time according to the query pattern and service description information; estimating node cost information of each processing node of a set of processing nodes in a computing system; selecting a processing node of the set of processing nodes according to the node cost information to allocate subtasks of the target task to the selected processing node; and determining an unallocated subtask in the target task to schedule the unallocated subtask according to the expected response time, the system cost information, and the estimated response time.

A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

The invention realizes miniaturization, high performance, and informatization of a control device. Only an application not required to be repeatedly executed with respect to a control subject at an execution interval less than or equal to a prescribed time interval is assigned to a fourth core (114) of a PLC (10).

A reconfigurable data processor comprises an array of configurable units configurable to allocate a plurality of sets of configurable units in the array to implement respective execution fragments of the data processing operation. Quiesce logic is coupled to configurable units in the array, configurable to respond to a quiesce control signal to quiesce the sets of configurable units in the array on quiesce boundaries of the respective execution fragments, and to forward quiesce ready signals for the respective execution fragments when the corresponding sets of processing units are ready. An array quiesce controller distributes the quiesce control signal to configurable units in the array, and receives quiesce ready signals for the respective execution fragments from the quiesce logic.