Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, in which each non-volatile memory package includes a plurality of non-volatile memory dies. The controller can select a non-volatile memory package with the switch. The controller can establish a data channel connection between the selected non-volatile memory package and the controller via the switch. In some aspects, the selected non-volatile memory package is transitioned into an active mode and one or more non-selected non-volatile memory packages are each transitioned into a standby mode. The controller also can perform one or more storage device operations with one or more non-volatile memory dies of the plurality of non-volatile memory dies within the selected non-volatile memory package. Thus, the controller may facilitate a switch based ball grid array extension, thereby improving memory capacity of the storage device.

A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

A method of sharing address information using quantum states includes storing a number, M, of first qubits in a quantum store at a source node and storing classical information tagged to the M first qubits in a classical store at the source node, where the classical information describes a destination node where the M first qubits share entangled qubits. The M first qubits are measured at the source node and a random number is generated that represents an address of the destination node using the measured M first qubits and the classical information describing the destination node. A packet is sent from the source node that includes the generated random number in a quantum address field and further includes data intended for the destination node in a data field. A number, M, of second qubits is stored in a quantum store at the destination node, wherein each of the M first qubits is entangled with a respective one of the M second qubits. The M second qubits is measured at the destination node and a random number is generated using the measured M second qubits. The sent packet is received at the destination node. The generated random number in the quantum address field is compared at the destination node with the generated random number using the measured M second qubits. A match is determined at the destination node between the compared generated random number in the quantum address field and the generated random number using the measured M second qubits.

Systems and methods data storage device performance prediction based on garbage collection resources are described. The data storage device may process host storage operations and determine a valid fragment count parameter for a current or future data block. Based on the valid fragment count parameter a predicted performance value for host storage operations is determined and the host device is notified of the predicted performance value.

An entangled quantum cache includes a quantum store that receives a plurality of quantum states and is configured to store and order the plurality of quantum states and to provide select ones of the stored and ordered plurality of quantum states to a quantum data output at a first desired time. A fidelity system is configured to determine a fidelity of at least some of the plurality of quantum states. A classical store is coupled to the fidelity system and configured to store classical data comprising the determined fidelity information and an index that associates particular ones of classical data with particular ones of the plurality of quantum states and to supply at least some of the classical data to a classical data output at a second desired time. A processor is connected to the classical store and determines the first time based on the index.

Techniques are disclosed relating to storing translations in memory that are usable to access data on a recording medium. In one embodiment, a request is sent for a memory allocation within a non-pageable portion of a memory in a computer system. Responsive to the request, allocated memory is received. Translations usable to map logical addresses to physical addresses within a storage device are stored within the allocated memory. In some embodiments, the translations are usable to access an area within the storage device used to store pages evicted from the memory. In one embodiment, a size of the memory allocation is determined based on a size of the area. In another embodiment, a size of the memory allocation is determined based on a size of a partition including the area. In some embodiments, the storage device is a solid-state storage array.

Memory is partitioned and isolated in container-based memory enclaves. The container-based memory enclaves have attestable security guarantees. During provisioning of the container-based memory enclaves from a container image, a purported link in the container to a memory address of the enclave is modified to verifiably link to an actual memory address of the host, such as partitioned memory enclave. In some instances, enclave attestation reports can be validated without transmitting corresponding attestation requests to remote attestation services, based on previous attestation of one or more previous container attestation reports from a similar container and without requiring end-to-end attestation between the container and remote attestation service for each new attestation request.

Systems and methods for a content addressable cache that is optimized for SSD use are disclosed. In some embodiments, the cache utilizes an identifier array where identification information is stored for each entry in the cache. However, the size of the bit field used for the identification information is not sufficient to uniquely identify the data stored at the associated entry in the cache. A smaller bit field increases the likelihood of a “false positive”, where the identification information indicates a cache hit when the actual data does not match the digest. A larger bit field decreases the probability of a “false positive”, at the expense of increased metadata memory space. Thus, the architecture allows for a compromise between metadata memory size and processing cycles.

A hypervisor that allocates the computer resource of a physical computer to one or more logical partitions allocates the computer resource to be allocated to the logical partitions to the logical partitions; generates, as address conversion information, the relationship between a guest physical address and a host physical address with respect to a memory of the computer resource; enables a first address conversion portion of a processor using the address conversion information; disables the first address conversion portion after the starting of a guest OS is completed; and causes an application to be executed.

An entangled quantum cache includes a quantum store that receives a plurality of quantum states and is configured to store and order the plurality of quantum states and to provide select ones of the stored and ordered plurality of quantum states to a quantum data output at a first desired time. A fidelity system is configured to determine a fidelity of at least some of the plurality of quantum states. A classical store is coupled to the fidelity system and configured to store classical data comprising the determined fidelity information and an index that associates particular ones of classical data with particular ones of the plurality of quantum states and to supply at least some of the classical data to a classical data output at a second desired time. A processor is connected to the classical store and determines the first time based on the index.