Various implementations described herein are directed to device. The device may include a first tier having a processor and a first cache memory that are coupled together via control logic to operate as a computing architecture. The device may include a second tier having a second cache memory that is coupled to the first cache memory. Also, the first tier and the second tier may be integrated together with the computing architecture to operate as a stackable cache memory architecture.

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.

An efficient structure and methodology are provided for implementing a dual-port memory module to provide improved memory capacity composability, expansion and sharing. This dual-port memory module uses high-speed SerDes or Optical based redundant access ports for connection to one or more CPUs or compute nodes, where each access port may access part or all of the module's memory capacity under configuration. This provides improvement for memory capacity composability, expansion through memory sharing and improved memory access performance and reliability for composable computing applications.

This invention relates to computer engineering and operating system components, in particular, it discloses a new method of building a hierarchal file system, which provides new functionality and flexibility, including: unlimited maximum possible file system size (number of elements), unlimited size of a single element, unlimited types of data, that can be represented as a file. In addition, the disclosed file system allows for user-defined types of data and can be used as a registry for OS system components, saving space important for resource-restricted embedded systems. The minimum file system size is 2 Bytes only. File system supports empty or non-unique files naming and natively provides built-in security using specification-based nodes header encoding. This result is achieved by using file systems nodes metadata comprising: the unique identifier (ID), an ASN.1 header with PER encoding, and a doubly linked list of logical blocks of its data. ID is of Unlimited Integer type and consist of 2 parts: preamble (extension bit) and Integer number. Nodes of a special types, for example, system nodes or nodes with new types defined by the developers of OS or related file system manager component, can utilize a special delegated processing. When reading and decoding a header of a node of a non-standard type, the file manager or utilities delegate processing of the node to a custom component that knows how to process this type of node.

Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.