An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

Systems and methods for explicit organization of memory allocation on an integrated circuit (IC) are provided. In particular, a programmable logic designer may incorporate specific mapping requests into programmable logic designs. The mapping requests may specify particular mappings between one or more data blocks (e.g., memory buffers) of a host program to one or more physical memory banks.

There is provided a method and apparatus of expanding capacity for a cache array. The method includes in response to detecting that a first new cache disk is to be added to a first cache array, initializing the first new cache disk without disabling other cache disks in the first cache array; allocating a storage space for a cache page metadata based on a result of the initializing; storing the cache page metadata into an initialized directory logical unit number, DIR LUN; storing a copy of the cache page metadata from a memory into the DIR LUN to facilitate the first cache disk to be in a ready state; and in response to the first new cache disk being in the ready state, configuring the first new cache disk as being in an initialized state to expand the capacity of the first cache array.

A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.

The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define and reconfiguration unit configured to define a memory as a required cache memory according to the configuration information; a control unit, configured to control writing and reading of the cache memory and monitor instructions and data streams in real time; a memory unit, composed of a number of memory modules and configured to cache data; the required cache memory is formed by memory modules according to the definition of the software define and reconfiguration unit; and an intelligence processing unit, configured to process input and output data and transfer, convert and operate on data among multiple structures defined in the control unit. The disclosure can realize an efficient memory system according to the operating status of software, the features of tasks to be executed and the features of data structures through the flexible organization and management by the control unit and the close cooperation of the intelligence processing unit.

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.

Systems and methods are configured for implementing a learning memory system organized as a network of multi-level and heterogeneous cues and dynamic association of cues with data units. In various embodiments, one or more hives are constructed within the memory system. Each hive is responsible for storing data of a particular modality. In addition, one or more localities are constructed for each hive. Each of the localities for a particular hive includes one or more data units that are semantically related and interconnected based on a relation to each other. Each of these data units contains a data element, features of the data element, and parameters relevant to the data element. Further, a cue bank is constructed for each hive to store cues configured to semantically link one or more data units across the various localities for a particular hive.

A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.