A semiconductor device includes: a first cache that includes a first memory and rewrite flags that indicate whether rewriting has been performed for each piece of data held in the first memory; and a second cache that includes a second memory and a third memory that has a lower writing speed than the second memory, stores data evicted from the first cache in the second memory when a rewrite flag corresponding to the evicted data indicates a rewrite state, and stores data evicted from the first cache in the third memory when a rewrite flag corresponding to the evicted data indicates a non-rewrite state.

A method and apparatus for allocating a memory address in a resource-centric network are disclosed. The method of allocating a memory address may include receiving a request for a new service, determining whether the new service is able to be accommodated in a virtual memory that is pre-allocated in a resource-centric network, when the new service is able to be accommodated, allocating a memory area for accommodating the new service to the virtual memory, and when the new service is not able to be accommodated, allocating the memory area by using an additionally allocated area of a virtual memory of the resource-centric network.

Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing rolling updates of distributed systems with a shared cache. An embodiment operates by receiving a data item key corresponding to a request from a user profile operating on a media player and receiving a version identifier corresponding to a first version of an application operating on the media player. It is determined that a shared cache includes a first value and second value for the data item key. A key component is generated corresponding to the user profile. Both the generated key component and the data item key are provided to the shared cache, and the first value of the data item as stored in the shared cache is received. The first value of the first version of the data item is updated.

A memory allocation manager and a method performed thereby for managing memory allocation, within a data centre, to an application are provided. The data centre comprises at least a Central Processing Unit, CPU, pool and at least one memory pool. The method comprises receiving (210) information associated with a plurality of instances associated with an application to be initiated, wherein individual instances are associated with individual memory requirements, the information further comprising information about an internal relationship between the instances; and determining (230) for a plurality of instances, a minimum number of memory blocks and associated sizes required based on the received information, by identifying parts of memory blocks and associated sizes that may be shared by two or more instances based on their individual memory requirements and/or the internal relationship between the instances. The method also comprises allocating (240) a number of memory blocks to the instances of the application based on the determined minimum number of memory blocks.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

Methods, computing systems and computer program products implement embodiments of the present invention that include identifying, in a storage system including multiple storage devices having respective sets of storage regions, respective default low storage region thresholds that are used for garbage collection. For each given storage region, a time threshold and an alternative low storage region threshold greater than the default low storage region threshold for the given storage device are defined. While processing input/output operations for each given storage device, a count of unused storage regions in the given storage device is maintained, a timer is initialized, and upon the timer matching the time threshold for the given storage device and upon the count of unused storage regions being less than or equal to the alternative low storage region threshold, a garbage collection operation is initiated. In some embodiments, processing the input/output operations includes using a log-structured array format.

A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients in accordance with the one or more bandwidth requirements.

Systems, methods, and apparatuses are directed to requesting access to a memory address; storing an identification of the memory address in a data structure; receiving a first request for access to the memory address, the request comprising a reference to a second processor core; storing the reference to the second processor in the data structure; receiving a second request for access to the memory address, the second request comprising a reference to a third processor core; determining, based on the data structure, that the third processor core is different from the second processor core; and responding to the second request without buffering the second request.

Utilizing a storage replica data structure includes receiving, at a hyper-kernel running on a computing node in a plurality of interconnected computing nodes, an indication of an operation pertaining to at least one of a guest physical memory address or a stable storage address. A guest operating system is run on a virtual environment that is defined by a set of hyper-kernels running on the plurality of interconnected computing nodes. It further includes updating a storage replica data structure. The storage replica data structure comprises a set of entries. The set of entries in the storage replica data structure comprises associations among guest physical memory addresses, physical memory addresses, and stable storage addresses

A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.