Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

A usage amount monitoring method is provided. The method may include: recording a usage amount time that records a maximum usage amount of the central processing unit (CPU) by recording a start time and an end time of task and interrupt service routine (ISR); storing data in a non-volatile memory by obtaining the maximum usage amount of the CPU, an engine revolutions per minute (RPM), a software operating mode, a fault code, a number of tasks started, and a task response time; and transmitting relevant information that is delivered to an external communication such that the relevant information may be confirmed in a personal computer (PC) in a chronological order after storing a previous record in the chronological order when the maximum usage amount of the CPU is updated.

A synthetic-aperture radar (SAR) antenna emits radar pulses and receives their reflections. SAR is typically used on a moving platform, such as an aircraft, drone, or spacecraft. Since the position of the antenna changes between the time of emitting a radar pulse and receiving the reflection of the pulse, the synthetic aperture of the radar is increased, giving greater accuracy for a same (physical) sized radar over conventional beam-scanning radar. The pulse data is processed, using a backprojection algorithm, to generate a two-dimensional image that can be used for navigation. The order in which the SAR data is processed can impact the likelihood of cache hits in accessing the data. Since accessing data from cache instead of memory storage reduces both access time and power consumption, devices that access more data from cache have greater battery life and range.

Systems, apparatuses, and methods related to media type selection are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and can write data to the memory media types. Data inputs can be written (e.g., stored) in a particular type of memory media based on characteristics (e.g., source, attributes, and/or information etc. included in the data). For instance, selection of memory media can be based on characteristics of the memory media type and the attributes of the data input. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, data from at least one of a plurality of sensors, identifying one or more attributes of the data; and selecting, based at least in part on the one or more attributes of the data, one or more of the memory media types to write the data to.

A communication method applied to a computer system that includes a first subsystem and a second subsystem. A safety level of the first subsystem is higher than a safety level of the second subsystem. The first subsystem includes a memory access checker. The method includes the memory access checker receives a memory access request from a memory access initiator, determines, based on preconfigured memory safety level division information, whether a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, and allows the memory access initiator to access the memory address when the safety level of the memory matches the safety level of the memory access initiator.

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

A method is described for calibrating a vehicle control unit, a data exchange taking place via a voltage supply line connected to the vehicle control unit, as well as a vehicle control unit, which is configured to carry out a data exchange for calibrating the vehicle control unit via a voltage supply line connected to the vehicle control unit with the aid of a communication signal (powerline communication) modulated to the supply voltage. A corresponding measuring and calibration system is also described.

Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.

Systems, apparatuses, and methods related to media type selection are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and can write data to the memory media types. Data inputs can be written (e.g., stored) in a particular type of memory media based on characteristics (e.g., source, attributes, and/or information etc. included in the data). For instance, selection of memory media can be based on characteristics of the memory media type and the attributes of the data input. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, data from at least one of a plurality of sensors, identifying one or more attributes of the data; and selecting, based at least in part on the one or more attributes of the data, one or more of the memory media types to write the data to.