The disclosed embodiments describe devices and methods for preventing unauthorized access to memory devices. The disclosed embodiments utilize a one-time programmable (OTP) memory added to both a memory device and a processing device. The OTP memory stores encryption keys and the encryption and decryption of messages between the two devices are used as a heartbeat to determine that the memory device has not been separated from the processing device and, in some instances, connected to a malicious processing device.

Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

The disclosed embodiments describe devices and methods for preventing unauthorized access to memory devices. The disclosed embodiments utilize a one-time programmable (OTP) memory added to both a memory device and a processing device. The OTP memory stores encryption keys and the encryption and decryption of messages between the two devices are used as a heartbeat to determine that the memory device has not been separated from the processing device and, in some instances, connected to a malicious processing device.

A data processor comprises a memory-management-unit for receiving external-operation-data from a CPU. The memory-management-unit sets a deterministic-quantity value for the external-operation-data based on the external-operation-data. The deterministic-quantity value may be either an active-value or an inactive-value. The data processor has a non-deterministic-processor-block for receiving a memory-signal from the memory-management-unit, and has a control-block configured to (i) send the memory-signal to an NDP-output-terminal if the deterministic-quantity value is the active-value, thereby bypassing a performance-enhancement-block, or (ii) send at least a portion of the memory-signal that is representative of the request for response-data to the performance-enhancement-block if the deterministic-quantity value is the inactive-value.

A method of caching large data objects of greater than 1 GB, comprising: populating a sharded cache with large data objects backfilled from a data store; servicing large data object requests from a plurality of worker nodes via the sharded cache, comprising deterministically addressing objects within the sharded cache; and if a number of requests for an object within a time exceeds a threshold: after receiving a request from a worker node for the object, sending the worker node a redirect message directed to a hot cache, wherein the hot cache is to backfill from a hot cache backfill, and wherein the hot cache backfill is to backfill from the sharded cache.

A vehicular device includes: a function processing unit that executes an application software; a volatile memory that temporarily stores a backup data; and a backup processing unit that copies the backup data from the volatile memory to a non-volatile memory when an event for terminating an operation occurs. The function processing unit and the backup processing unit execute processes independently, and are accessible to a same memory space in the volatile memory, respectively. The function processing unit reads out the backup data from the volatile memory and reboots the application software when an event for maintaining an activation occurs while the backup processing unit is storing the backup data from the volatile memory to the non-volatile memory.

An apparatus for controlling autonomous driving of a vehicle is introduced. The apparatus may generate profiling data comprising an access count of each of a plurality of sections, wherein the plurality of sections are associated with at least one task performed for an operation control of the vehicle. The apparatus may determine, based on the profiling data, a priority for each of the plurality of sections. Further, the apparatus may assign, based on the priority, the plurality of sections to one or more of a plurality of storage devices included in the memory, output, based on the sequentially assigned plurality of sections, a signal for the operation control of the vehicle, and control, based on the signal, an operation of autonomous driving of the vehicle.

A usage amount monitoring method is provided. The method may include: recording a usage amount time that records a maximum usage amount of the central processing unit (CPU) by recording a start time and an end time of task and interrupt service routine (ISR); storing data in a non-volatile memory by obtaining the maximum usage amount of the CPU, an engine revolutions per minute (RPM), a software operating mode, a fault code, a number of tasks started, and a task response time; and transmitting relevant information that is delivered to an external communication such that the relevant information may be confirmed in a personal computer (PC) in a chronological order after storing a previous record in the chronological order when the maximum usage amount of the CPU is updated.

A control device for a motor vehicle, the control device including at least two processor cores and a global memory, each processor core respectively including a local memory and each processor core being set up to access only its own local memory and being set up to access neither the local memories of the other processor cores nor the global memory, a coordination unit being set up to read in data from the global memory of the control device and to write it to the local memories of the individual processor cores, and to read in data from the local memories of the individual processor cores and to write it to the global memory and/or to the local memory of the other processor cores.

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.