The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

Disclosed are a device and method for realizing data synchronization. The device may include a synchronization circuit for a plurality of radio frequency (RF) chips, configured to realize work clock synchronization among the plurality of RF chips; and/or, a synchronization circuit for a plurality of channels in a single chip, configured to realize data synchronization among the plurality of channels in the single chip.

The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.

A system and method for improving the management of data input and output (I/O) operations for Shingled Magnetic Recording (SMR) devices in a network storage system is disclosed. The storage system includes a storage controller that receives a series of write requests for data blocks to be written to non-sequential addresses within a pool of SMR devices. The storage controller writes the data blocks from the series of write requests to a corresponding sequence of data clusters allocated within a first data cache of the storage controller for a thinly provisioned volume of the pool of SMR devices. Upon determining that a current utilization of the first data cache's data storage capacity exceeds a threshold, the sequence of data clusters including the data blocks from the first data cache are transferred to sequential physical addresses within the SMR devices.

Aspects of the inventive concept relates to a method of accessing a storage device including a nonvolatile memory device and a controller. The method includes writing user data, a first logical address and a second logical address associated with the user data in a storage space corresponding to the first logical address of the nonvolatile memory device. The user data is update data that updates previous data written in the nonvolatile memory device. The second logical address is a logical address of a storage space of the nonvolatile memory device in which the previous data is written.

Host memory buffer is dynamically adjusted based on performance. As memory pages are accessed, one or more counts of the memory pages are maintained. If the counts indicate some of the memory pages are identical, then a portion of host system memory allocated to buffer cache may be reduced or decremented in response to repetitive access. However, if the counts indicate different memory pages are accessed, then the host system memory allocated to the buffer cache may be increased or incremented.

A first non-volatile memory may store first data and a second non-volatile memory may store second data. An authentication component may be coupled with the first non-volatile memory and the second non-volatile memory and may receive a request to perform an authentication operation. In response to the request to perform the authentication operation, the authentication component may access the first data stored at the first non-volatile memory and the second data stored at the second non-volatile memory and determine whether the second data stored at the second non-volatile memory has become unreliable based on a memory disturbance condition. In response to determining that the second data stored at the second non-volatile memory has become unreliable, a corrective action associated with the first data stored at the first non-volatile memory may be performed.

In one embodiment, repetitive address indirection is employed to repetitively redirect write operations to different physical locations of the memory. In one embodiment, write data for every write operation is automatically, unconditionally and repetitively redirected to physical addresses in a memory in a circular sequence of physical addresses of the memory independently of, that is without regard to, the logical address of each write operation. As a result, successive write operations to the memory are automatically evenly distributed over the memory, even if repeatedly directed to the same or similar logical address. Other aspects are described herein.

A semiconductor storage device has a non-volatile memory, a memory controller to carry out write processing to the non-volatile memory using a write pulse, and a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory,