A method of updating a program code of an electronic device is disclosed. An existing firmware or software is originally stored in a first memory of the electronic device. The electronic device gradually generates a plurality of parts of an updated version of the existing firmware according to a patch file and the existing firmware, and gradually updates the firmware or software of the electronic device in a piece-by-piece fashion. A memory size of the electronic device is reduced.

The present invention provides a DRAM/NVM hierarchical heterogeneous memory system with software-hardware cooperative management schemes. In the system, NVM is used as large-capacity main memory, and DRAM is used as a cache to the NVM. Some reserved bits in the data structure of TLB and last-level page table are employed effectively to eliminate hardware costs in the conventional hardware-managed hierarchical memory architecture. The cache management in such a heterogeneous memory system is pushed to the software level. Moreover, the invention is able to reduce memory access latency in case of last-level cache misses. Considering that many applications have relatively poor data locality in big data application environments, the conventional demand-based data fetching policy for DRAM cache can aggravates cache pollution. In the present invention, an utility-based data fetching mechanism is adopted in the DRAM/NVM hierarchical memory system, and it determines whether data in the NVM should be cached in the DRAM according to current DRAM memory utilization and application memory access patterns. It improves the efficiency of the DRAM cache and bandwidth usage between the NVM main memory and the DRAM cache.

Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.

Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. AnHBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.

An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared.

A vehicular display device includes: a display means; a control means for controlling the display of the display means; a non-volatile memory for storing at least an operation program for the control means or image data to be displayed on the display means; and a third connection terminal that can be connected with either a first connection terminal or a second connection terminal having different terminal arrangements. The vehicular display device, housed in an instrument panel of a vehicle, is provided with an external device that communicates with the control means by connecting the first connection terminal or the second connection terminal to the third connection terminal, wherein the control means determines whether over-writing of the non-volatile memory should be allowed in accordance with the type of the connection terminal connected to the third connection terminal.

A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.

The present invention provides a data storage device including a flash memory and a controller. The controller distributes TLC-data blocks of the flash memory into three regions, obtains three sub-prewrite data sectors according to a prewrite data sector and a logic address, determines a first TLC-data block according to the logic address, selects a new first TLC-data block with the lowest erase count from the first region when the first TLC-data block has valid data, selects two TLC-data blocks according to the new first TLC-data block, writes the three sub-prewrite data sectors into the new first TLC-data block and the two selected TLC-data blocks, and maps the first new TLC-data block and the two selected TLC-data blocks to the logic address.

A volatile/non-volatile memory device access provisioning system includes a processing system and a controller coupled to a memory device. The controller provides an access key to the memory device and causes memory device communications to be passed to the processing system when the access key is available. The controller simply causes memory device communications to be passed to the processing system when the access key is not available. The memory device masks non-volatile memory subsystem access information in the memory device to prevent the processing system from accessing non-volatile memory subsystem(s) in the memory device, and then determines whether the access key has been received from the controller. The memory device will unmask the non-volatile memory subsystem access information such that the processing system can access non-volatile memory subsystem(s) in response to determining that the access key has been received from the controller.