A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.

An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared.

The invention relates to retrieving data from a storage system. One embodiment of the invention comprises receiving a write operation, establishing a correspondence relationship between a logic block address and a physical block address of the write operation, and determining whether a valid data percentage in a mapping table is greater than a predetermined threshold after the correspondence relationship is added in stored metadata of stored metadata.

A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, where current data to be written to a nonvolatile memory corresponds to an address cache hit is determined. If the current data to be written corresponds to an address cache hit, the current data are written to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to an address cache miss, the current data are written to the destined location in the nonvolatile memory. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

An apparatus includes an interface and a processor. The interface is configured to communicate with a non-volatile memory. The processor is configured to hold a translation table that maps between logical addresses and respective physical addresses in the non-volatile memory, to back-up to the non-volatile memory a baseline version of the translation table in one or more bulks, to additionally back-up to the non-volatile memory one or more incremental updates, which specify changes relative to the baseline version of the translation table caused by subsequent storage operations, to determine a maximal number of the incremental updates that, when recovered together with the baseline version from the non-volatile memory and replayed in the processor, meets a target recovery time of the translation table, and to set a number of the backed-up incremental updates to not exceed the maximal number.

A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the named portion to the logical addresses defined for the entire non-volatile storage media.

A memory device may include: a data determination unit for receiving page data from a main memory device, and distinguishing between first and second data based on tag information of the page data; an index management unit for storing an index of the first data; a first cache for storing the second data, and writing back first victim data to the main memory device, the first victim data being selected when the first cache is full; and a second cache for storing the first victim data transferred from the first cache when a write count of the first victim data is smaller than a first threshold value, updating tag information of second victim data to a value indicating the first data, the second victim data being selected when the second cache is full, and storing the second victim data in the main memory device.

A memory controller controls a nonvolatile memory having physical blocks. The memory controller includes a control unit and a host interface unit. The control unit writes data into a physical block. The host interface unit receives and transmits data from and to the external device. The control unit manages first vacant blocks and second vacant blocks based on a physical-block management table for managing states of the physical blocks. The first vacant block can be used in garbage collection processing of arranging data stored in the nonvolatile memory. The second vacant block cannot be used in garbage collection processing. The control unit increases a quantity of the second vacant blocks when the control unit does not receive an instruction from the external device. The control unit writes data into the second vacant blocks when the control unit receives an instruction for writing data from the external device.