Methods, systems, and devices supporting techniques for pre-fetching information using pattern detection are described. Some memory systems may support pre-fetching information, such as logical-to-physical (L2P) mapping tables, data, or both, if a sequential pattern of read commands is detected. In some examples, the memory system may store a list of logical addresses indicated by received read commands and may determine whether the list corresponds to a sequential pattern independent of intervening write-alike commands. The list may store previous logical addresses for read commands, allowing the memory system to determine whether subsequent read commands form a sequential pattern. Additionally or alternatively, the memory system may track a ratio of hibernate commands to other commands (e.g., sequential read commands) and may refrain from pre-fetching L2P mapping tables for a detected sequence if the tracked ratio satisfies (e.g., exceeds) a threshold ratio.

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

A memory system includes a first volatile memory having an access unit of a first bit width; a second volatile memory having an access unit of the first bit width and having a capacity larger than the first volatile memory; and a controller connected to the first and second volatile memories. The controller allocates a first address space having the first bit width as a unit to the first volatile memory, allocates a second address space having the first bit width as a unit to the second volatile memory, selects at least one of the first and second volatile memories based on a first address indicating a position in a third address space having a second bit width as a unit, calculates a second address in the address space allocated to the selected volatile memory, and accesses a position corresponding to the second address of the selected volatile memory.

Disclosed are a solid state drive and a write operation method. The solid state drive comprises: a controller, receiving write data from outside and comprising a first cache unit for storing the write data; a Flash memory, receiving the write data sent by the first cache unit according to a first instruction of the controller; a second cache unit, storing the write data from the first cache unit as backup data, and sending the backup data to the Flash memory according to a second instruction of the controller. The second instruction is obtained after the write data fails to be written into the Flash memory under the first instruction, so that the backup data can continue to be called if write operation fails. By combining advantages of the first and second cache units, efficiency and quality of write operations are improved and bandwidth requirements are lowered.

Methods, systems, and devices for configurable flush operation speed are described. Before executing a flush operation at a first portion of a cache including single-level cells (SLCs), a memory system may communicate parameters associated with data stored in the first portion of the cache to a host system. The host system may then identify another portion of the cache (e.g., including either SLCs or multi-level cells (MLCs)) for the flush operation based on the parameters and a speed of a flush operation associated with the other portions of the cache. The host system may indicate the identified portion of the cache to the memory system and the memory system may execute a flush operation at the first portion of the cache. For example, the memory system may write a subset of the data stored at the first portion of the cache to a second portion of the cache.

A non-volatile data storage device includes memory cells arranged in a plurality of blocks and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to determine if a given block is a bad m-bit multi-level block. In an m-bit multi-level block, each memory cell is an m-bit multi-level cell (MLC), m being an integer equal to or greater than 2. Upon determining that the given block is a good m-bit multi-level block, the memory controller assigns the given block to be an m-bit multi-level user block. Upon determining that the given block is a bad m-bit multi-level block, the memory controller determines if the given block is a good n-bit block. In an n-bit block, each memory cell is an n-bit cell, n being an integer less than m. Upon determining that the given block is a good n-bit block, the memory controller assigns the given block to be an n-bit user block or an n-bit write-buffer block.

A method for block addressing is provided. The method includes moving content of a data block referenced by a logical block address (LBA) from a first physical block corresponding to a first physical block address (PBA) to a second physical block corresponding to a second PBA, wherein prior to the moving a logical map maps the LBA to a middle block address (MBA) and a middle map maps the MBA to the first PBA and in response to the moving, updating the middle map to map the MBA to the second PBA instead of the first PBA.

Provided are a computer program product, integrated cache manager, and method for maintaining data in a first level memory and buckets representing regions of memory devices to extend data cache. A plurality of buckets represent distinct regions of memory devices. The buckets are associated with different threshold access count ranges. Data having an access count is stored in one of the buckets associated with a threshold access count range including the access count of the data to store. Data evicted from a first level memory is copied to an initial bucket comprising one of the buckets. Data is moved from a source bucket comprising one of the buckets, including the initial bucket, to a target bucket of the buckets having a target threshold access count range including an access count of the data to move.

A technique performs data reduction on host data of a write request during ingest under certain circumstances. Therein, raw host data of a write request is placed from the host into a data cache. Further, a data reducing ingest operation is performed that reduces the raw host data from the data cache into reduced host data (e.g., via deduplication, compression, combinations thereof, etc.). After completion of the data reducing ingest operation, performing a late-binding operation is performed that updates a mapper with ability to access the reduced host data from secondary storage. Such ingest-time data reduction may be enabled/disabled (e.g., turned on or off) per input/output (I/O) operation (e.g., used only for relatively large asynchronous I/O operations) and/or activated in situations in which the ingest bandwidth is becoming a bottleneck.

Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.