According to one general aspect, an apparatus may include a host interface layer, a translation data structure, and a non-volatile memory. The host interface layer may be configured to receive a multi-association command that associates two or more keys with a common value. The translation data structure may be configured to: maintain a key-value index that represents a plurality of key-value descriptors stored within a non-volatile memory, and associate the two or more keys with the common value. The non-volatile memory configured to store a plurality of key-value descriptors each including a respective value and at least one respective key, wherein at least one key-value descriptor includes a plurality of keys, wherein each of the plurality of keys are associated with the common value, and wherein the at least one key-value descriptor further includes either the common value or a pointer to the common value.

Methods and apparatuses for data transformation are disclosed. An exemplary apparatus includes a first memory, a second memory, a cross-bar switch communicatively coupled between the first memory and the second memory, and a lookup table that specifies one or more memory addresses of the first memory to read out to the cross-bar switch, one or more memory addresses of the second memory to which to write data from the cross-bar switch, and a configuration of the cross-bar switch. An exemplary method includes determining, based on a lookup table, one or more memory addresses of a first memory to read out to a cross-bar switch, determining, based on the lookup table, one or more memory addresses of a second memory to which to write data from the cross-bar switch, and determining, based on the lookup table, a configuration of the cross-bar switch.

The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

A data accessing method includes: determining whether a preset cache area has cached data that a read target address points to when receiving a read instruction that includes the read target address; and finding a cache address corresponding to the read target address according to a first mapping relationship if the preset cache area has cached the data that the read target address points to, and reading data that the cache address points to from the preset cache area, where the first mapping relationship is used to record a correspondence between the target address and the cache address; orreading, from non-volatile storage space, the data that the read target address points to if the preset cache area has not cached the data that the read target address points to. By means of the method, data read errors caused by write interference can be reduced.

A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.

A method for using an access triggered architecture for a computer implemented application is provided. The method receives a set of data at a designated functional block associated with a system memory location; performs an operation at the designated functional block, using the set of data, to generate a result, wherein the operation is performed each time information is received at the designated functional block; and returns the generated result to the system memory location.

Techniques for accessing off-heap memory are disclosed. The system may receive a memory segment layout definition for a memory segment in a physical memory of a machine. The memory segment layout definition defines a number of elements and a number of sub-elements in each element of the plurality of elements. The system may allocate the particular memory segment in the physical memory and may store a reference to a position of a sub-element. The system may receive a request to access a first sub-element of a particular element of the plurality of elements. Based on the request, the system may identify the memory segment corresponding to the plurality of elements, identify the particular element of the plurality of elements, identify the first sub-element of the plurality of elements based the position of the first sub-element, and execute an Input or Output (IO) operation corresponding to the request.

Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods are disclosed. In certain aspects, memory controllers are employed that can provide memory capacity compression. In certain aspects disclosed herein, a next read address prefetching scheme can be used by a memory controller to speculatively prefetch data from system memory at another address beyond the currently accessed address. Thus, when memory data is addressed in the compressed memory, if the next read address is stored in metadata associated with the memory block at the accessed address, the memory data at the next read address can be prefetched by the memory controller to be available in case a subsequent read operation issued by a central processing unit (CPU) has been prefetched by the memory controller.

Monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by the processor. The processor executes a transactional memory (TM) transaction, including receiving, by the processor, a memory address range of data that a co-processor may access to perform a co-processor operation. The processor saves the memory address range. Based on receiving, by the processor, a cache coherency request that conflicts with the saved address range, the processor aborts the TM transaction.

A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.