A processing-in-memory (PIM) device includes a data selection circuit, a multiplying-and-accumulating (MAC) circuit, and an accumulative adding circuit. The data selection circuit generates selection data from input data and zero-point data based on a zero-point selection signal. The MAC circuit performs a MAC arithmetic operation for the selection data to generate MAC result data. The accumulative adding circuit accumulatively adds MAC sign data based on a MAC output latch signal to generate MAC latch data. A sign of the MAC sign data is determined by the zero-point selection signal.

A cache coherence management system includes: a set of directories distributed between nodes of a network for interconnecting processors including cache memories, each directory including a correspondence table between cache lines and information fields on the cache lines; and a mechanism updating the directories by adding, modifying, or deleting cache lines in the correspondence tables. In each correspondence table and for each cache line identified, at least one field is provided for indicating a possible blocking of a transaction relative to the cache line considered, when the blocking occurs in the node associated with the correspondence table considered. The system further includes a mechanism detecting fields indicating a transaction blocking and restarting each transaction detected as blocked from the node in which it is indicated as blocked.

A data processing system is disclosed, which relates to a technology for implementing a convergence memory system provided with a plurality of memories. The data processing system includes a compute blade configured to generate a write command to store data and a read command to read the data, and a memory blade configured to selectively performed read and write operations in response to the read and write commands in a plurality of memories. The compute blade has a memory that stores information about performance characteristics of each of the plurality of memories, and is configured to determine priority information through which eviction of a cache line is carried out based on the stored information.

A disaggregated memory system includes a plurality of compute nodes, each including at least one local memory device configured to fulfill at least some of a plurality of memory read requests and memory write requests for the compute node. A disaggregated memory pool includes a plurality of memory devices each physically separate from the plurality of compute nodes. The disaggregated memory pool is configured to supplement the at least one local memory device of each of the plurality of compute nodes by fulfilling at least some of the plurality of memory read requests and memory write requests of each of the plurality of compute nodes at any particular memory device of the disaggregated memory pool. An amount of memory collectively allocated to the plurality of compute nodes exceeds an amount of memory collectively provided by the plurality of memory devices.

Disclosed herein is a persistent memory (PMEM)-based distributed memory object system, referred to as the PMEM DMO system, that provides affordable means of integrating low-latency PMEM spaces with other devices, including servers that do not directly support PMEM. One embodiment comprises providing a cluster of servers with PMEM storage (PMEM servers) and connecting the PMEM servers to a plurality of applications servers using a low-latency network, such as a remote direct memory access; background processes on each of the application servers are tasked to perform input/output operations for the application servers to locally materialize objects from and synchronize/persist objects to the remote PMEM spaces on the PMEM servers. Data materialized from the PMEM servers is stored to the local cache of the application server for use. Also disclosed are data eviction policies for clearing the local cache of the application servers to make space for new data read.

In one aspect of the present description, a primary-secondary role swap operation which swaps roles of primary and secondary data storage systems in a distributed data storage system, is synchronized with safe data commit scan operations of individual data storage systems. The safe data commit scan operations of the individual data storage systems are also synchronized to ensure completion of the safe data commit scans and to reduce the occurrence of reductions in input/output (I/O) response times prior to initiation of a primary-secondary role swap operation. Other features and aspects may be realized, depending upon the particular application.

A memory management process monitors a communication channel for messages comprising allocation data corresponding to a first discrete memory region and receives a message comprising the allocation data. The memory management process executes a memory management decision for the first discrete memory region based on the allocation data, wherein the first discrete memory region is not addressable by the processing device.

An illustrative embodiment disclosed herein is an object store with distributed caching including a distributed cache cluster including a first cache on a first node device and a second cache on a second node device. The object store with distributed caching further includes a gateway server communicatively coupled to the distributed cache cluster. The gateway server receives a request to store an object from a client device, determines whether the object satisfies an object policy, determines whether the request indicates that the object is to be split up into a plurality of shards, and stores a first shard of the plurality of shards in the first cache and a second shard of the plurality of shards in the second cache.

An illustrative embodiment disclosed herein is an object store with distributed caching including a distributed cache cluster including a first cache on a first node device and a second cache on a second node device. The object store with distributed caching further includes a gateway server communicatively coupled to the distributed cache cluster. The gateway server receives a request to store an object from a client device, determines whether the object satisfies an object policy, determines whether the request indicates that the object is to be split up into a plurality of shards, and stores a first shard of the plurality of shards in the first cache and a second shard of the plurality of shards in the second cache.

Direct inter-processor communication is enabled with respect to data in a memory location without having to switch specific circuits through a switching element (e.g., an optical switch). Rather, in this approach a memory pool is augmented to include a dedicated portion that serves as a disaggregated memory common space for communicating processors. The approach obviates the requirement of switching of physical memory modules through the optical switch to enable the processor-to-processor communication. Rather, processors (communicating with another) have an overlapping ability to access the same memory module in the pool; thus, there is no longer a need to change physical optical switch circuits to facilitate the inter-processor communication. The disaggregated memory common space is shared among the processors, which can access the common space for reads and writes, although particular locations in the memory common space for reads and writes are different.